RISC-V Certification Test Plan Draft Proposal

Contributors to all versions of the spec in alphabetical order

Jordan Carlin
James Kaden Cassidy
David Harris
Georgia Tai

This document is released under a Creative Commons Attribution 4.0 International License.

This is a draft Certification Test Plan. It reflects the coverpoints and tests presently being developed in the cvw-arch-verif repository soon to migrate to riscv-arch-test cvw branch. It is intended for discussion as a possible format of test plan for RISC-V Certification.

1. Introduction

This Certification Test Plan describes the coverpoints and tests to certify RISC-V profiles. It summarizes the profiles intended to be supported and the test suites that need to run on each profile. It also summarizes the contents of each test suite.

1.1. Coverpoints and Tests

Coverpoints are the key to certification. They are the features of the RISC-V architecture that need to be tested in order to certify a profile. Each coverpoint has a set of tests that exercise it, and each test has a set of coverpoints that it hits.

This test plan defines the coverpoints that must be hit for each profile, and outlines the tests that hit those coverpoints. The tests are self-checking, and report pass/fail results. The coverage report confirms that the tests hit all the coverpoints.

Coverpoints are written in SystemVerilog, and are designed to be used with the Extended RISC-V Verification Interface (RVVI). They are written to be independent of the DUT (Device Under Test), so that they can be used with any RISC-V implementation. ^[1] Functional coverage is collected using SystemVerilog infrastructure adapted from riscvISACOV ^[2].

Coverpoints are organized into .svh SystemVerilog coverage files, each of which contain one or more covergroups, each of which contain one or more coverpoints. Coverage files apply to a DUT with a particular set of extensions. For example, the I_coverage.svh coverage file is used for any 32 or 64-bit DUT that supports the I extension. The ZicsrM_coverage.svh coverage file applies to a DUT that supports the Zicsr extension and machine mode. The ZicsrS_coverage.svh coverage file applies to a DUT that supports the Zicsr extension and supervisor mode.

Tests are written in assembly language .S files.Tests are organized into directories for each extension, and into a privileged directory. The coverpoints are hit by running all of the applicable tests in a directory. For example, RV32I coverage involves running add.S, addi.S, sub.S, etc. RV64I coverage also involves running addw.S, which is unique to RV64.

The tests need to perform basic system-level functions, such as booting the DUT, sending interrupts, and logging results. These functions are performed by a "trick box" that is implemented in DUT-specific macros. The trick box is described in Chapter 8.

1.2. Glossary

The following terms are used in this test plan:

Extensions: named and ratified RISC-V extensions, such as RV32I, M, Zbb, or Zicsr.
Parameters: options describing the behavior of extensions. Parameters may or may not have an official RISC-V name. For example, the Sm machine mode extension defines Physical Memory Protection, which has a named parameter G defining the granularity and an unnamed parameter indicating 0, 16, or 64 PMP regions. The Sv* virtual memory extensions have additional Svade and Svadu extensions, which are parameters defining whether setting the Accessed and Dirty bits is done with a page fault exception or by the Hardware Page Table Walker. There is a completely unnamed parameter defining whether misaligned exceptions have higher or lower priority than access-fault exceptions. Parameters will eventually all have formal names in UDB when they are all identified.
Configuration: A set of extensions and parameters partially or fully describing the behavior of a RISC-V hart. A full configuration is sufficient for a reference model to exactly match the behavior of a DUT except with regard to non-deterministic behaviors.
Non-deterministic Behaviors: behaviors that are unpredictable despite a full configuration. For example, a tail-agnostic vector instruction might copy vector elements from the source, or might provide elements that are all 1s. Either behavior is correct, and the hart might change behaviors from one instruction to the next, so the DUT and reference model cannot be guaranteed to exactly match. Self-checking tests must accept all legal outcomes for non-deterministic behaviors.
Profile: A named collection of required and optional extensions, such as RVI20 or RVA23S64. Profiles may be ratified by RISC-V or developed by the Certification Steering Committee to meet certification market needs, such as a simple microcontroller. A profile is a partial configuration. The test plan must allow the DUT configuration to indicate which optional extensions and other parameters are used, and fully test all optional profile extensions provided by the DUT.
UDB: Unified Database, a standardized way to describe the configuration and generate config files for various tools from a single point of truth.
Normative rule: Description of a single certifiable feature, preferably a direct quotation from a ratified specification.
Coverage files: a SystemVerilog .svh file containing all of the covergroups for an extension or combination of extensions, such as I_coverage.svh or ZfaD_coverage.svh.
Covergroup: A SystemVerilog construct that contains one or more coverpoints. Covergroups are used to collect functional coverage of a particular feature or set of features in the RISC-V architecture. For example, the I_coverage.svh file contains a covergroup for each instruction in the I extension, such as add, addi, sub, etc. The InterruptsM_coverage.svh contains a single InterruptsM_cg covergroup with all the coverpoints for machine-mode interrupts.
Coverpoint: A SystemVerilog construct describing a set of conditions to test. For example, the cp_rd coverpoint checks that all 32 destination registers x0-x31 are exercised by instructions that don’t trap. Each coverpoint has one or more bins; for example, cp_rd has 32 bins for the different registers.
Bin: One target value for a coverpoint. Each bin may be covered or not by a test suite.
Test files: A file containing one or more tests, typically written in assembly language. For example, rv32/I/add.S contains all of the RV32 tests to exercise the add_cg covergroup in I_coverage.svh.
Test: A snippet of code, typically a sequence of assembly language instructions, that exercises at least one bin of a coverpoint.
Test Suite: A collection of coverage and test files to test a particular extension, combination of extensions, or group of extensions. For example, the RV32I test suite contains the I_coverage.svh coverage file and the rv32/I/add.S, addi.S, sub.S, and other tests files with tests that hit the coverpoints in that coverage file. The RV64ZfaD test suite contains the ZfaD_coverage.svh coverage file and the rv64/ZfaD/fround.d.S, and other tests files with tests that hit the coverpoints in that coverage file. The RVA23S64 test suite contains all of the required and selected optional test suites for the profile, incluidng RV64I, RV64ZfaD, ExceptionsS, etc.
Trick Box: A set of DUT-specific macros that perform non-ISA functions such as booting the DUT, sending interrupts, and logging results. The trick box is defined in Chapter 8.

Beware that Test Suite is also used outside this document to mean a full set of tests for a given profile from a given provider. For example, Synopsys, Breker, and riscv-arch-test all have test suites for the RVI20U32 profile.

2. Certification Process

Certifying a RISC-V Device-Under-Test (DUT) involves the following steps:

Selecting a profile for the DUT
Providing a Unified Database (UDB) configuration for the DUT, such as optional extensions, peripheral addresses, and PMP granularity
Generating self-checking tests based on the selected profile and UDB
Running the tests and reporting pass/fail

Test developers also need to

Generate a coverage report confirming that the tests hit all the coverpoints based on a Sail trace

3. Profiles & Test Suites

This test plan addresses Phase 0, Phase 1, and Phase 2 RISC-V certification objectives, including the following ratified and unratified profiles:

RVI20 Profile (Ratified): Phase 0
- RV{32/64}IMAFDC_Zifencei_Zicntr_Zihpm with machine mode, no PMP
Microcontroller Profile (Not Ratified, but market demand): Phase 1
- RV{32/64}IMZca_Zcb_Zifencei_Zicsr_Zicntr with machine mode, user mode, interrupts, PMP16 ^[3]
RVA22S64 Profile (Ratified): Phase 1.5, stepping stone to phase 2
- Application processor without vector, hypervisor, and other newer extensions
RVB23S64 Profile (Ratified): Phase 1.8, stepping stone to phase 2
- RVA23 less vector and hypervisor
RVA23S64 Profile (Ratified): Phase 2

3.1. Profile Coverage Matrix

Table 1 summarizes the coverage files applicable to each profile. x indicates a mandatory extension, and o indicates an optional extension. The certification test plan handles all mandatory and optional extensions.

Coverage files with multiple extensions in the name apply when all the extensions are supported; for example, ZfaZfhD is used in a system supporting Zfa, Zfh, and D extensions.

All privileged suites require at least version 1.12 of the privileged specification. Features specific to version 1.13 are tested separately in the Sm1p13 and Ss1p13 suites.

Table 1. Profile Coverage Files
Coverage File	Description	Test Plan	RVI20	uController	RVA22S64	RVB23S64	RVA23S64
XLEN			32/64	32	64	64	64
Unprivileged
I	Integer	Table 10	x	x	x	x	x
M	Mult/Div	Table 14	o	x	x	x	x
Zmmul	Mult Only	Table 16
Zaamo	Atomic Memory Ops	Table 34	o	x	x	x	x
Zalrsc	Load Reserved / Store Cond	Table 36	o	x	x	x	x
Zca	Compressed	Table 19	o	x	x	x	x
Zcb	Extra Compressed	Table 25		x		x	x
ZcbM	Compressed Multiply	Table 27		x		x	x
ZcbZba	Compressed Zero Extend	Table 29		x		x	x
ZcbZbb	Compressed Sign Extend	Table 31		x		x	x
Zcf	Compressed Float	Table 21	o
Zcd	Compressed Double	Table 23	o		x	x	x
F	Float	Table 38	o		x	x	x
D	Double	Table 39	o		x	x	x
Zfh	Half	Table 40			o	o	o
ZfhD	Half-Double Converts	Section 5.7.3.2			o	o	o
Zfhmin	Half Converts	Table 41			x	o	x
ZfhminD	Half-Double Converts	Table 42			x	o	x
ZfaF	Additional Float	Table 43				x	x
ZfaD	Additional Double	Table 44				x	x
ZfaZfh	Additional Half	Table 45				o	o
ZfaZfhD	Additional Half-Double Converts	Table 46				o	o
Zba	Address Generation	Table 48		x	x	x	x
Zbb	Basic Bit Manipulation	Table 49		x	x	x	x
Zbc	Carryless Multiplication	Table 50					o
Zbs	Single-Bit	Table 51		x	x	x	x
Zbkb	Bit Manip for Crypto	Table 52		o		o
Zbkc	Carryless Multiply for Crypto	Table 53				o
Zbkx	Permutations	Table 54				o
Zknd	AES Decryption	Table 56				o
Zkne	AES Encryption	Table 55				o
Zknh	SHA2 Hashing	Table 57				o
Zicsr	CSR Instructions	Table 58			x	x	x
Zicond	Conditional Move	Table 60				x	x
Zifencei	Instruction Fence	Table 59	o	x	x	x	x
Zihintpause	Pause Hint	Table 61			x	x	x
Zihintntl	Nontemporal Locality Hint	Table 62				x	x
ZihintntlZca	Compressed Nontemporal Locality Hint	Table 63				x	x
Zicbom	Cache Block Flush/Inval	Table 64			x	x	x
Zicboz	Cache Block Zero	Table 65			x	x	x
Zicbop	Cache Block Prefetch	Table 66			x	x	x
Za64rs	Max 64B Reservation Sets	Table 67			x	x	x
Zic64bZicboz	64B Cache Blocks	Table 68			x	x	x
Privileged
ZicsrM	Machine CSRs	Table 98		x	x	x	x
ZicsrS	Supervisor CSRs	Table 99			x	x	x
ZicsrU	User CSRs	Table 100		x	x	x	x
ZicsrF	Float CSRs	Table 101	o		x	x	x
ZicsrUF	User Float CSRs	Table 103			x	x	x
ZicsrZkr	Entropy CSR	Table 105			o	o	o
ExceptionsM	Machine Exceptions	Table 106		x	x	x	x
ExceptionsS	Supervisor Exceptions	Table 107			x	x	x
ExceptionsU	User Exceptions	Table 108		x	x	x	x
ExceptionsF	Float Exceptions	Table 109		x	x	x	x
ExceptionsZalrsc	LR/SC Exceptions	Table 111		x	x	x	x
ExceptionsZaamo	AMO Exceptions	Table 112		x	x	x	x
ExceptionsZc	Compressed Exceptions	Table 113		x	x	x	x
ExceptionsZicboS	Supervisor CBO Exceptions	Table 114			x	x	x
ExceptionsZicboU	User CBO Exceptions	Table 115			x	x	x
ExceptionsVM	Virt Mem Exceptions	Table 116			x	x	x
ExceptionsVMZalrsc	Virt Mem LR/SC Exceptions	Table 117			x	x	x
ExceptionsVMZaamo	Virt Mem AMO Exceptions	Table 118			x	x	x
Zicclsm	Misaligned Loads / Stores	Table 119			x	x	x
InterruptsM	Machine Interrupts	Table 120		x	x	x	x
InterruptsS	Supervisor Interrupts	Table 121			x	x	x
InterruptsU	User Interrupts	Table 122		x	x	x	x
InterruptsSstc	Supervisor Timer Compare	Table 123			x	x	x
ZicntrM	Machine Counters	Table 124	o	x	x	x	x
ZicntrS	Supervisor Counters	Table 125			x	x	x
ZicntrU	User Counters	Table 126		x	x	x	x
Zihpm	Hardware Performance Monitors	Table 127	o	x	x	x	x
EndianM	Machine Endian	Table 128
EndianS	Supervisor Endian	Table 129
EndianU	User Endian	Table 130
EndianZaamo	AMO Endian	Table 131
EndianZalrsc	LR/SC Endian	Table 132
PMPM	Machine PMP	Table 136		x	x	x	x
PMPS	Supervisor PMP	Table 137			x	x	x
PMPU	User PMP	Table 138		x	x	x	x
PMPF	Float PMP	Table 139			x	x	x
PMPZca	Compressed PMP	Table 140			x	x	x
PMPZicbo	PMP + CBOM/CBOZ	Table 141			x	x	x
PMPZaamo	AMO PMP	Table 142			x	x	x
PMPZalrsc	LR/SC PMP	Table 143			x	x	x
Svbare	No Virtual Memory	Table 144			x	x	x
Sv	Sv32/39/48/57 Virtual Memory	Table 145
Svinval	TLB Invalidation	Table 148			x	x	x
VMPMP	VM + PMP	Table 146			x	x	x
VMZicbo	VM + CBOM/CBOZ	[t-VMZicbo-coverpoints]			x	x	x
VMPMPZicbo	VM + PMP + CBOM/CBOZ	Table 147			x	x	x
Svade	Page Table A/D Exceptions	Table 149			x	x	x
Svadu	Page Table Update	Table 150				o	o
Svpbmt	Page-based Memory Types	Table 151			x	x	x
Svnapot	Naturally Aligned Pages	Table 152			o	x	x
Sscofpmf	Counter Filtering	Table 185			o	x	x
Ssstateen	Supervisor State Enable	Table 186			o		x
Ssu64xl	64-bit UXL	Table 187			o	x	x
Sscounterenw	Counter Enables Writable	Table 188			x	x	x
Sstvecd	Direct Vector	Table 189			x	x	x
Sstvala	stval Addresses	Table 190			x	x	x
Strict
SsstrictM	Machine Strict (unratified)	Table 133			o	o	o
SsstrictS	Superisor Strict	Table 134			o	o	o
Vector
Vx8	Vector Integer 8-bit	Table 70			o	o	x
Vx16	Vector Integer 16-bit	Table 70			o	o	x
Vx32	Vector Integer 32-bit	Table 70			o	o	x
Vx64	Vector Integer 64-bit	Table 70			o	o	x
Vls8	Vector Load/Store 8-bit	Table 71			o	o	x
Vls16	Vector Load/Store 16-bit	Table 71			o	o	x
Vls32	Vector Load/Store 32-bit	Table 71			o	o	x
Vls64	Vector Load/Store 64-bit	Table 71			o	o	x
Vf16 (Zvfh)	Vector Float 16-bit	Table 72				o	o
Vf32	Vector Float 32-bit	Table 72			o	o	x
Vf64	Vector Float 64-bit	Table 72			o	o	x
Zvfhmin	Vector half conversions	Table 73				o	o
Zvfbfmin	Vector BF16 Convert	Table 75				o	o
Zvfbfwma	Vector BF16 MAC	Table 76				o	o
Zvfhmin	Vector half conversions	Table 73				o	o
ZfaZvfh	fli for Vector Half	Table 74				o	o
Zvbb8	Vector Bit Manip 8-bit	Table 77				o	x
Zvbb16	Vector Bit Manip 16-bit	Table 77				o	x
Zvbb32	Vector Bit Manip 32-bit	Table 77				o	x
Zvbb64	Vector Bit Manip 64-bit	Table 77				o	x
Zvkb8	Vector Crypto Bit Manip 8-bit	Table 79				o	o
Zvkb16	Vector Crypto Bit Manip 16-bit	Table 79				o	o
Zvkb32	Vector Crypto Bit Manip 32-bit	Table 79				o	o
Zvkb64	Vector Crypto Bit Manip 64-bit	Table 79				o	o
Zvbc64	Vector Carryless Mult	Table 78				o	o
Zvkg32	Vector GCM	Table 80				o	o
Zvkned32	Vector Crypt	Table 81				o	o
Zvknha32	Vector Hash 32-bit	Table 82
Zvknhb64	Vector Hash 64-bit	Table 82				o	o
Vector Privileged
ExceptionsV	Vector Exceptions	Table 110			o	o	x
ZicsrV	Vector CSRs	Table 102			o	o	x
ZicsrUV	User Vector CSRs	Table 104			o	o	x
SsstrictV	Vector Strict	Table 135			o	o	o
Hypervisor
H	Hypervisor Instructions	Table 153			o	o	x
ZicsrH	Hypervisor CSRs	Table 154			o	o	x
ExceptionsH	Hypervisor Exceptions	Table 155			o	o	x
ExceptionsHV	Hypervisor Vector Exceptions	Table 156			o	o	x
InterruptsH	Hypervisor Interrupts	Table 157			o	o	x
EndianH	Hypervisor Endian	Table 158			o	o	x
ZicntrH	Hypervisor Counters	Table 159			o	o	x
PMPH	Hypervisor PMP	Table 160			o	o	x
VMH	Hypervisor Virtual Memory	[t-VMH-coverpoints]			o	o	x
VMHCBO	Hypervisor Virtual Memory + CBO	[t-VMHCBO-coverpoints]			o	o	x
Shcounterenw	Counter Enables	Table 165			o	o	x
Shvsatpa	VM Modes Supported	Table 166			o	o	x
Shgatpa	VM x4 Modes Supported	Table 167			o	o	x
Shvstvecd	Direct Vectoring	Table 168			o	o	x
Shvstvala	vstval Addresses	Table 169			o	o	x
Shtvala	htval Addresses	Table 170			o	o	x
Shlcofideleg	Counter Overflow Delegation	Table 171			o	o	x
ZkrH	Hypervisor Entropy	Table 172			o	o	x
SstcH	Hypervisor Supervisor Timer	Table 173			o	o	x
SsstateenH	Hypervisor State Enable	Table 174			o	o	x
SscrindH	Hypervisor Indirect CSR	Table 175			o	o	x
SscfgH	Hypervisor Counter Delegation	Table 176			o	o	x
SmctrH	Hypervisor Control Transfer Records	Table 177			o	o	x
SvinvalH	Hypervisor TLB Inval	Table 178			o	o	o
SvaduH	Hypervisor TLB Update	Table 179			o	o	o
ZicfilpH	Hypervisor Landing Pad	Table 180			o	o	o
ZicfissH	Hypervisor Shadow Stack	Table 181			o	o	o
SsdbltrpH	Double Trap	Table 182			o	o	o
SsnpmH	Pointer Masking	Table 183			o	o	o
SmnpmH	Pointer Masking	Table 184			o	o	o
Miscellaneous RV{A/B}23 Extensions
Ss1p13	Supervisor 1p13	Table 191				x	x
Ssnpm	Pointer Masking	Table 192				x	x
Smnpm	Pointer Masking	Table 193
Smmpm	Pointer Masking	Table 194
Zacas	Atomic Compare-And-Swap	Table 83				o	o
Zabha	Subword Atomics	Table 84				o	o
Zicfilp	Landing Pads	Table 195				o	o
Zicfiss	Shadow Stack	Table 196				o	o
Zfbfmin	BF16 Convert	Table 47				o	o
Zimop	Maybe-Ops	Table 85				x	x
Zcmop	Compressed Maybe-Ops	Table 86				x	x
Zawrs	Wait on Reservation Set	Table 197				x	x
Sdtrig	Debug Triggers	Table 198				o	o
Other Recent Extensions
Zfinx	Float in Int Regs	Table 87
Zdinx	Double in Int Regs	Table 88
Zhinx	Half in Int Regs	Table 89
Zhinxmin	Half Cvt in Int Regs	Table 90
Zcmp	Compressed Push/Pop	Table 91
Zcmt	Compressed Table Jumps	Table 92
Zilsd	Load/Store Double	Table 93
Zclsd	Compressed Load/Store Double	Table 94
Smcsrind	Machine Indirect CSRs	Table 201
Sscsrind	Supervisor Indirect CSRs	Table 202
Smepmp	Enhanced PMP	Table 203
Smrnmi	Machine Resumable Interrupts	Table 204
Ssrnmi	Supervisor Resumable Interrupts	Table 205
Sm1p13	Machine 1p13	Table 199				x	x
Smstateen	Machine State Enable	Table 200
Smcntrpmf	Cycle and Instret Mode Filtering	Table 206
Smcdeleg	Counter Delegation	Table 207
Ssccfg	Counter Delegation	Table 208
Smdbltrp	Machine Double Trap	Table 209
Ssdbltrp	Supervisor Double Trap	Table 210
Smctr	Control Transfer Records	Table 211
Ssqosid	Quality-of-Service ID	Table 212
Embedded
E	Embedded 16 Regs	E Instruction Coverpoints
EM	Multiply/Divide	EM Instruction Coverpoints
EZmmul	Multiply	[t-EZmmul-coverpoints]
EZca	Compressed	EZca Instruction Coverpoints
EZcb	Additional Compressed	EZcb Instruction Coverpoints
EZcmp	Compressed Push/Pop	EZcmp Instruction Coverpoints
EZcmt	Compressed Table Jump	EZcmt Instruction Coverpoints
EZba	Address Generation	EZba Instruction Coverpoints
EZbb	Bit Manipulation	EZbb Instruction Coverpoints
EZbs	Single-Bit	EZbs Instruction Coverpoints
Debug
DM	Debug Module	Table 213
DTM	Debug Transport Module	Table 214
Sdext	Debug Mode	Table 215
Advanced Interrupt Architecture
Smaia	Machine Advanced Interrupts	Table 216
Ssaia	Supervisor Advanced Interrupts	Table 217
IMSIC	Incoming MSI Controller	Table 218
APLIC	Advanced Platform-Level Interrupt Controller	Table 219
IOMMU	AIA I/O Memory Management Unit	Table 220
I/O Memory Management Unit
IOMMU	I/O Memory Management Unit	Table 220

3.2. Architecturally Untestable Extensions

Table 2 lists certain extensions whose behavior is not readily visible at the architectural level of observed program behavior, such as constant-time instructions and PMAs. These are outside the scope of certification. PMA properties are implicitly tested by executing instructions that depend on the property, but not tested comprehensively across the entire memory map.

Table 2. Extensions Lacking Architectural Visibility for Certification Testing
Coverage File	Description	RVA22S64	RVB23S64	RVA23S64
Ziccif	Main memory PMA supports instruction fetch	x	x	x
Ziccrse	Main memory PMA supports RsrvEventual	x	x	x
Ziccamoa	Main memory PMA supports atomics	x	x	x
Ziccamoc	Main memory PMA supports AMOCASQ		x	x
Zama16b	Main memory PMPA supports misaligned atomics within 16-byte regions			x
Zkt	Constant-time scalar crypto	x	x	x
Zvkt	Constant-time vector crypto	x	x	x
Svvptc	Valid PTEs appear within bounded time without fence		x	x

3.3. Certification Requirements

Certification places basic requirements on the DUT.

3.3.1. Conforming M-Mode

The privileged testplan relies on a machine mode conforming to Sm1p12 machine architecture or later. The tests need to configure machine-mode CSRs that affect the behavior of lower privilege modes. This is done most easily by directly writing such registers using standard instructions in machine mode. It is theoretically possible to write tests that only operate in S and U-mode, and use some sort of generalized SBI interface to request machine mode configurations even from non-conforming machine-mode implementations, but no such SBI interface exists at this time and the complexity seems to exceed the benefit. Therefore, privileged tests rely on machine-mode, and also contain coverpoints and tests to check that privileged behaviors work correctly in machine mode.

3.3.2. Consistent XLEN and Endianness

The test plan requires that after the boot process, XLEN and endianness are the same in all privilege modes. Specifically, MXLEN = SXLEN = UXLEN = HSXLEN = VSXLEN and MBE = SBE = UBE = VSBE. If this is not the reset state of the DUT, the RVMODEL_BOOT trick box macro may be able to place it in that state before testing. If the DUT cannot be placed in this state, it cannot be certified because the tests assume XLEN and endianness do not change with privilege mode unless specifcially modified by a test. For example, a machine hardwired to 64-bit machine mode and 32-bit user mode is not certifiable. (Presently, only endian changes are tested; certifying multiple XLEN is not a priority.)

4. General Test Plan Strategy

This CTP describes tests for all supported RISC-V profiles, but the tests run on a specific DUT. The DUT configuration is described with RISC-V Unified Database, and supplementary files such as simulator configuration files are automatically generated from the UDB so there is a single configuration file to maintain. The UDB describes the supported extensions, and also has parameters defining optional behaviors of those extensions. If a behavior is UNSPECIFIED in the specification, it is not tested because there are no wrong answers. A common purpose of parameters is to define the behavior of WARL fields in CSRs.

4.1. Configuration

The DUT is described with a Unified Database (UDB) YAML file. This file lists:

all of the supported extensions
all of the parameters required to describe the behavior of the extensions

The DUT also needs to know how to boot the core, terminate a test with a success code, send a message to a console, and cause interrupts. These DUT-specific behaviors are described by a Trick Box, which is an assembly-language library implementing an API using DUT-specific hardware.

is a linker script really needed? For PMP?

4.2. Unified Database

Unified Database allows partially- and fully-configured descriptions. A profile is an example of a partially configured description because it has a mix of required and optional extensions, and does not specify parameter values for most of the extensions. A DUT needs to have a fully configured description including precisely which versions of which extensions are supported and what parameter values are implemented, so that a simulator can exactly match its behavior.

The certification framework requires a fully-configured UDB description of the DUT and a trick box for the DUT. It uses UDB to produce supplementary configuration files including:

Sail JSON file configuring reference model to match DUT
Configuration files for other optional simulators, such as Spike, ImperasFPM
SystemVerilog coverage.svh file describing which coverage files and parameter values to use for coverage measurement
Optional DUT configuration files (CORE-V Wally Example) providing parameter values to configurable RTL

4.2.1. Configuration Parameters

The UDB parameters for each extension are defined in:

github.com/riscv-software-src/riscv-unified-db/tree/main/spec/std/isa/ext

The CSC Tests and Models working group developed the following list of configuration parameters. Need to check if they match the parameters in UDB extensions.

docs.google.com/spreadsheets/d/1tFGLbocTp1YNn11aN8JTmvxL_23e7x8SlBNJfOPRmAE/edit?gid=0#gid=0

A partially-configured UDB description of each profile is given in:

RVI20U32
RVI20U64
MC100
RVA22S64
RVB23S64
RVA23S64
- add minimal and maximal fully configured flavors of these profiles in riscv-arch-test, with no and all optional features, and suitable parameters.

4.3. Unspecified and Reserved Behaviors

Some RISC-V behaviors are UNSPECIFIED, which means an implementation can do anything. These behaviors are not tested because there is no wrong answer. Table 3 summarizes the normative rules regarding reserved behaviors.

Unimplemented opcodes (except in the custom space) and instructions accessing non-existent CSRs are reserved. The behavior of reserved instructions is UNSPECIFIED, so they should not be tested by most testplans. However, when the Ssstrict extension is enabled, reserved instructions raise an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler. This is tested by the Ssstrict test plan.

Table 3. I Normative Rules Regarding Behaviors
Spec Section	Normative Rule
Unpriv 1.7	The term UNSPECIFIED refers to a behavior or value that is intentionally unconstrained.
Unpriv 2.2	For this purpose, we divide each RISC-V instruction-set encoding space (and related encoding spaces such as the CSRs) into three disjoint categories: standard, reserved, and custom. … Reserved encodings are currently not defined but are saved for future standard extensions; once thus used, they become standard encodings. … The behavior upon decoding a reserved instruction is UNSPECIFIED.
Privileged 2.1	Instructions that access a non-existent CSR are reserved.
rva23-profile	Ssstrict No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.

4.4. CSR Bitfields

CSR fields can be Write Preserves, Read Ignores (WPRI), Write Legal, Read Legal (WLRL), or Write Any, Read Legal (WARL). Examples of WPRI fields include undefined fields of xstatus, xenvcfg, mseccfg, and xstateen* that could have unintended side effects if they are subsequently defined and unwittingly set to nonzero values. Examples of WLRL fields include xcause.ExceptionCode and hstatus.VGEIN. Other CSR fields are generally WARL.

WPRI fields are not tested. WLRL fields are tested with all legal values but no illegal values. WARL fields are tested by trying all possible values of the field. CSR tests (Section 6.2) generally involve setting all bits to 1, setting all to 0, and writing walking 1s. Therefore, they inherently exercise all possible values of 1 and 2-bit WARL fields. Longer fields can be tested exhaustively if the number of possibilities is small (such as satp.MODE), or just with walking 1s if the number of possibilities is too large (such as misa.EXTENSIONS).

Table 4 summarizes the normative rules regarding CSR bitfields.

Table 4. I Normative Rules Regarding Bitfields
Spec Section	Normative Rule
Privileged 2.3	Some whole read/write fields are reserved for future use. Software should ignore the values read from these fields, and should preserve the values held in these fields when writing values to other fields of the same register. For forward compatibility, implementations that do not furnish these fields must make them read-only zero. These fields are labeled WPRI in the register descriptions.
Privileged 2.3	Some read/write CSR fields specify behavior for only a subset of possible bit encodings, with other bit encodings reserved. Software should not write anything other than legal values to such a field, and should not assume a read will return a legal value unless the last write was of a legal value, or the register has not been written since another operation (e.g., reset) set the register to a legal value. These fields are labeled WLRL in the register descriptions.
Privileged 2.3	Implementations are permitted but not required to raise an illegal-instruction exception if an instruction attempts to write a non-supported value to a WLRL field. Implementations can return arbitrary bit patterns on the read of a WLRL field when the last write was of an illegal value, but the value returned should deterministically depend on the illegal written value and the value of the field prior to the write.
Privileged 2.3	Some read/write CSR fields are only defined for a subset of bit encodings, but allow any value to be written while guaranteeing to return a legal value whenever read. Assuming that writing the CSR has no other side effects, the range of supported values can be determined by attempting to write a desired setting then reading to see if the value was retained. These fields are labeled WARL in the register descriptions.
Privileged 2.3	Implementations will not raise an exception on writes of unsupported values to a WARL field. Implementations can return any legal value on the read of a WARL field when the last write was of an illegal value, but the legal value returned should deterministically depend on the illegal written value and the architectural state of the hart.

should there be a parameter about WLRL fields throwing illegal instruction when an illegal value is written?

4.5. Normative Rules

The testplan for each extension contains a list of normative rules applicable to that extension. Normative rules are generally direct quotations from a ratified RISC-V specification describing a single certifiable feature. They are associated with an ID anchor in the ASCIIDoc source of the spec. Normative rules only apply to statements that could be measured by a test. In particular, introductory overview and non-normative explanatory text is not quoted as a normative rule. For brevity, there are no normative rules associated with instruction opcodes, CSR numbers, or similar encodings; these are tested when the instruction is executed or CSR is accessed.

Occasionally, the rule is implicit in the specification, such as the artwork of a figure or the logical interaction of multiple quotations from a spec. Such rules are fabricated in this test plan, and supported by references to figures or by a combination of quotations and some logical reasoning. * link to an example where this is needed, if needed

4.6. Normative Rule IDs

Normative rule IDs follow the format defined in the UDB documentation. Table 5 provides examples

Table 5. Normative Rule ID Examples
Scenario	Example	Rule
Instruction	`norm:inst:add:operation`	ADD performs the addition of rs1 and rs2.
Several Instructions	`norm:insts:slt_sltu:operation`	SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise.
CSR	`norm:csr:hstatus:reg`	The hstatus register is an HSXLEN-bit read/write register formatted as shown in when HSXLEN=32 and when HSXLEN=64. The hstatus register provides facilities analogous to the mstatus register for tracking and controlling the exception behavior of a VS-mode guest.
Several CSRs	`norm:csrs:sie_hip_hie:mutex`	For each writable bit in sie, the corresponding bit shall be read-only zero in both hip and hie. Hence, the nonzero bits in sie and hie are always mutually exclusive, and likewise for sip and hip.
CSR bitfield	`norm:csrfld:hstatus:vsxl:op`	The VSXL field controls the effective XLEN for VS-mode (known as VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN). When HSXLEN=32, the VSXL field does not exist, and VSXLEN=32. When HSXLEN=64, VSXL is a WARL field that is encoded the same as the MXL field of misa, shown in . In particular, an implementation may make VSXL be a read-only field whose value always ensures that VSXLEN=HSXLEN.
Other behaviors not in the schema	`norm:ext:H:vscsrs-vs-perm`	When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual-instruction exception.

The following code snippets show how to tag the spec.

Normative rule IDs can be applied to an entire paragraph with a [[norm:…]] ID.

[[norm:instgrp:load_store:endian_byte_operation]]
In a system for which endianness is byte-address invariant, the
following property holds: if a byte is stored to memory at some address
in some endianness, then a byte-sized load from that address in any
endianness returns the stored value.

Alternatively, they can be applied to a portion of a paragraph:

#[#norm:...]#tagged text#

[#norm:inst:add:operation]#ADD performs the addition of _rs1_ and
_rs2_.#[#norm:inst:sub:operation]#SUB performs the subtraction of _rs2_ from _rs1_.#[#norm:insts:add_sub:overflow]#Overflows are ignored and the low XLEN bits of results are written to the destination _rd_.#

need to choose operation vs. op
level of detail: regularly subtag sentences or subsentence in a paragraph

4.7. Coverpoints

Coverpoints are written with one file that covers both RV32 and RV64, to reduce the duplication and risk of becoming out of sync. When a coverage file contains coverpoints that apply only to one XLEN or the other (e.g. 32 or 64-bit edge values), they are separated by ifdef XLEN32` or XLEN64 directives. Similarly, when a coverpoint applies only to a certain parameter value (PMP NA4 regions are not supported for granularity coarser than 4 bytes), they uses ifdef`` to exclude tests based on the parameter value.

4.8. Tests

Privileged tests are mostly written by hand and share a single .S file that can be compiled for either RV32 or RV64, again with ifdef directives to separate the two. Unprivileged tests are generated from a template using a Python script, and are divided into RV32 and RV64 directories because the random values differ with XLEN.

no loops - each test should have a unique PC?

5. Unprivileged Test Plan

Unprivileged tests exercise every instruction using every applicable source and destination register, and reasonable architectural edge values of sources. They are intended for certification, not verification. For example, they do not test all difficult floating-point cases.

The unprivileged test plan is written to be easily reviewed by a human, and to be automatically converted to machine-readable coverpoints and tests. It is defined with spreadsheets in comma-separated value (CSV) format.

5.1. Unprivileged Tests

Every bin in every coverpoint is associated with a specific test ^[4]. Unprivileged tests sweep some feature under test (such as the destination register rd) while randomizing all applicable register IDs and source values (including values to be loaded from memory). For example, the unprivileged test for the cp_rd coverpoint of the add instruction contains 32 add instructions, using the 32 different choices of rd. The rs1 and rs2 register numbers and values are selected randomly. [Appendix A: Examples] gives examples of unprivileged coverpoints and tests meeting these requirements and the coverpoints of Table 10 for the add instruction. Each test is self-checking, checking the destination register value against one provided by a reference model. Certain tests also test other state such as stores or floating-point flags, as described in those sections.

The random values are preferably selected in a deterministic way so that regenerating tests use the same random values where possible, minimizing differences between tests. This can be done by seeding the random number generator with a has of the instruction and coverpoint name.

Unprivileged tests are designed to never trap. Their results are independent of the privilege mode in which they are run, so they generally are run only in machine mode. They generally involve no privileged instructions, except that floating-point and vector tests turn on the mstatus.{FS/VS} bits to enable these extensions.

5.2. Unprivileged Coverpoints

The coverpoints in Table 6 are used in most of the unprivileged test plans in subsequent sections.

Table 6. Coverpoint Definitions
Coverpoint	Bins	Definition
Basic Coverpoints
cp_asm_count	1	Number of times the instruction is executed in the test, must be greater than 0.
cp_rs1	32	The rs1 register number used in the instruction.
cp_rs2	32	The rs2 register number used in the instruction.
cp_rd	32	The rd register number used in the instruction.
cp_rs1_edges	16	Edge values for rs1 (see Table 7).
cp_rs2_edges	16	Edge values for rs2 (see Table 7).
cp_imm_edges	16	Edge values for 12-bit immediates (see Table 8).
cr_rs1_imm_edges	16*20	Cross-product of rs1 and 12-bit immediate edges (see Table 8).
cr_rs1_rs2_edges	16*16	Cross-product of rs1 and rs2 edges, used for instructions with two source registers.
cmp_rs1_rs2	32	The rs1 and rs2 registers have the same register number.
cmp_rd_rs1	32	The rd register has the same register number as the rs1 register.
cmp_rd_rs2	32	The rd register has the same register number as the rs2 register.
cmp_rd_rs1_rs2	32	The rd register has the same register number as both the rs1 and rs2 registers.
cp_offset	2	A branch or jalr instruction has a positive and negative offset.
cp_uimm	`XLEN`	Exercise all XLEN unsigned immediate values, such as shift amounts.
cp_align	≤ 8	Alignment of naturally-aligned sub-doubleword load/store operand within doubleword
cp_gpr_hazard	4	General-purpose register hazard detection: RAW, WAR, WAW, and no hazard.
Coverpoints for Compressed Instructions
cp_rs1p	8	The rs1 register number used in compressed instructions supporting x8-x15.
cp_rs2p	8	The rs2 register number used in compressed instructions supporting x8-x15.
cp_rdp	8	The rd register number used in compressed instructions supporting x8-x15.
cp_fdp	8	The fd register number used in compressed floating-point instructions supporting x8-x15.
cp_fs2p	8	The fs2 register number used in compressed floating-point instructions supporting x8-x15.
cp_imm_mul	8	7-bit immediate that is a multiple of 4 (for word-sized load/store instructions).
Coverpoints for Floating-Point Instructions
cp_fs1	32	The fs1 register number used in the instruction.
cp_fs2	32	The fs2 register number used in the instruction.
cp_fs3	32	The fs3 register number used in the instruction.
cp_fd	32	The fd register number used in the instruction.
cp_fs1_edges	26	Edge values for fs1 (see Table 9)
cp_fs2_edges	26	Edge values for fs2 (see Table 9)
cp_fs3_edges	26	Edge values for fs3 (see Table 9)
cmp_fd_fs1	32	The fd register has the same register number as the fs1 register.
cmp_fd_fs2	32	The fd register has the same register number as the fs2 register.
cmp_fd_fs3	32	The fd register has the same register number as the fs3 register.
cp_frm	5	The floating-point rounding mode used in the instruction: rne, rdn, rup, rtz, rmm, dyn.
cp_csr_fflags	10	The instruction sets the {NV, DZ, OF, UF, NX} flags in the fflags CSR.
cp_csr_frm	6	Dynamic rounding mode in the frm CSR: rne, rdn, rup, rtz, rmm, illegal
cr_fs1_fs2_edges	26*26	Cross product of edges of fs1 and fs2 registers.
cr_fs1_fs3_edges	26*26	Cross product of edges of fs1 and fs3 registers.
cp_fclass	10	All 10 fclass classes.
cp_NaNBox	1	Upper bits of NaN-boxed value are all 1s
cp_fs1_badNB	12	The fs1 register contains an incorrectly-NaN-boxed lower-precision value.
cp_fs2_badNB	12	The fs2 register contains an incorrectly-NaN-boxed lower-precision value.
cp_fs3_badNB	12	The fs3 register contains an incorrectly-NaN-boxed lower-precision value.
cp_fpr_hazard	4	Floating-point register hazard detection: RAW, WAR, WAW, and no hazard.
Miscellaneous Coverpoints
cp_bs	4	Byte select field for 32-bit AES instructions
cp_rnum	11	Round nummber for AES instructions
cp_sc	2	Store conditional instruction has a success and failure case.

Notes:

These coverpoints are adapted from the Imperas riscvISACOV functional coverage project.
Register number is a 5-bit ID (e.g. x7), while register value is an XLEN-sized number.
Most coverpoints typically have 32 bins because they exercise all 32 integer registers.
Cross-products exercise all combinations of two or more coverpoints. They can have a large number of bins.
Each of these coverpoints can optionally have a modifer appended. For example, cp_rs1_nx0 is a modified version of cp_rs1, covering all 31 rs1 register numbers excluding x0. It is used for load/store/jalr instructions that can’t rely on address 0 specified by x0 being legal. Modifiers are defined in the extensions that they apply to.
The cmp_* and cp_*_hazard coverpoints occupy the fuzzy land at the edge of certification and verification. They are included because they are easy.
The riscvISACOV test plan had cmp_rd_{rs1/rs2}_eqval coverpoints that compare if rd and one of the sources have the same value. These are generally hit by the cr_rs1_rs2_edges tests, so they don’t add interesting additional coverage and were dropped. riscvISACOV also had cp_{rs1/rs2/rd}_toggle tests that checked if each bit changed from 1 to 0 and vice versa. This is trivially exercised by providing all 0s followed by all 1s followed by al 0s again, so they were dropped.

Table 7. Integer Edge Case Definitions
Bin	RV32	RV64
zero	`00000000000000000000000000000000`	`0000000000000000000000000000000000000000000000000000000000000000`
one	`00000000000000000000000000000001`	`0000000000000000000000000000000000000000000000000000000000000001`
two	`00000000000000000000000000000010`	`0000000000000000000000000000000000000000000000000000000000000010`
min	`10000000000000000000000000000000`	`1000000000000000000000000000000000000000000000000000000000000000`
minp1	`10000000000000000000000000000001`	`1000000000000000000000000000000000000000000000000000000000000001`
max	`01111111111111111111111111111111`	`0111111111111111111111111111111111111111111111111111111111111111`
maxm1	`01111111111111111111111111111110`	`0111111111111111111111111111111111111111111111111111111111111110`
ones	`11111111111111111111111111111111`	`1111111111111111111111111111111111111111111111111111111111111111`
onesm1	`11111111111111111111111111111110`	`1111111111111111111111111111111111111111111111111111111111111110`
walkeodd	`10101010101010101010101010101010`	`1010101010101010101010101010101010101010101010101010101010101010`
walkeven	`01010101010101010101010101010101`	`0101010101010101010101010101010101010101010101010101010101010101`
random	`01???????????????????????????010`	`01???????????????????????????????????????????????????????????010`
Wmax	n/a	`0000000000000000000000000000000011111111111111111111111111111111`
Wmaxm1	n/a	`0000000000000000000000000000000011111111111111111111111111111110`
Wmaxp1	n/a	`0000000000000000000000000000000100000000000000000000000000000000`
Wmaxp2	n/a	`0000000000000000000000000000000100000000000000000000000000000001`

Table 8. Immediate Edge Case Definitions (12-bit)
Bin	12-bit Signed Value
zero	0
p0	1
p1	2
three	3
p2	4
p3	8
p4	16
p5	32
p6	64
p7	128
p8	256
p9	512
hm1	1023
p10	1024
max	2047
min	-2048
minp1	-2047
onesm1	-2
ones	-1
randomp	1795

Table 9. Floating-Point Edge Case Definitions
Bin	Half	Float	Double
pos0	`0000`	`00000000`	`0000000000000000`
neg0	`8000`	`80000000`	`8000000000000000`
pos1	`3C00`	`3F800000`	`3FF0000000000000`
neg1	`BC00`	`BF800000`	`BFF0000000000000`
pos1p5	`3E00`	`3F000000`	`3FE0000000000000`
neg1p5	`BE00`	`BF000000`	`BFE0000000000000`
pos2	`4000`	`40000000`	`4000000000000000`
neg2	`C000`	`C0000000`	`C000000000000000`
posminnorm	`0400`	`00800000`	`0010000000000000`
negminnorm	`8400`	`80800000`	`8010000000000000`
posmaxnorm	`7BFF`	`7F7FFFFF`	`7FEFFFFFFFFFFFFF`
negmaxnorm	`FBFF`	`FF7FFFFF`	`FFEFFFFFFFFFFFFF`
posmax_subnorm	`03FF`	`007FFFFF`	`000FFFFFFFFFFFFF`
negmax_subnorm	`83FF`	`807FFFFF`	`800FFFFFFFFFFFFF`
posmid_subnorm	`0200`	`00400000`	`0008000000000000`
negmid_subnorm	`8200`	`80400000`	`8008000000000000`
posmin_subnorm	`0001`	`00000001`	`0000000000000001`
negmin_subnorm	`8001`	`80000001`	`8000000000000001`
posinfinity	`7C00`	`7F800000`	`7FF0000000000000`
neginfinity	`FC00`	`FF800000`	`FFF0000000000000`
posQNaN	`7E00`-`7FFF`	`7FC00000`-`7FFFFFFF`	`7FF8000000000000`-`7FFFFFFFFFFFFFFF`
posSNaN	`7C01`-`7DFF`	`7F800001`-`7FBFFFFF`	`7FF0000000000001`-`7FF7FFFFFFFFFFFF`
negQNaN	`FE00`-`FFFF`	`FFC00000`-`FFFFFFFF`	`FFF8000000000000`-`FFFFFFFFFFFFFFFF`
negSNaN	`FC01`-`FDFF`	`FF800001`-`FFBFFFFF`	`FFF0000000000001`-`FFF7FFFFFFFFFFFF`
posrandom	`58B4`	`7ef8654f`	`3FF58B4C00000000`
negrandom	`C93A`	`813d9ab0`	`A6E895993737426C`

The register edge cases are selected to include extreme values and their immediate neighbors. They also include walking 1s and a random number to exercise intermediate values. RV64 adds edge casess near the 32-bit boundary to stress W-type instructions. Immediate edge cases exercise each bit of the immediate, extreme values, and one random intermediate value.

5.3. I Base Integer Extension

Table 10 summarizes the coverpoints for the I extension. The Type column is used to generate tests with the appropriate operands. An x in the RV32 or RV64 colunn indicates that the instruction is supported in that XLEN. The remaining columns refer to coverpoints defined in Table 6.

Table 10. I Instruction Coverpoints
Instruction	add	addi	addiw	addw	and	andi	auipc	beq	bge
Type	R	I	I	R	R	I	U	B	B
RV32	x	x			x	x	x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x		x	x
cp_rs2	x			x	x			x	x
cp_rd	x	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x		x	x
cp_rs2_edges	x			x	x			x	x
cr_rs1_imm_edges		x	x			x
cr_rs1_rs2_edges	x			x	x			offset	offset
cmp_rs1_rs2	x			x	x			x	x
cmp_rd_rs1	x	x	x	x	x	x
cmp_rd_rs2	x			x	x
cmp_rd_rs1_rs2	x			x	x
cp_offset								x	x
cp_imm_edges		x	x			x	20bit	branch	branch
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	w	r	r

Instruction	bgeu	blt	bltu	bne	jal	jalr	lb	lbu	ld
Type	B	B	B	B	J	JR	L	L	L
RV32	x	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x		nx0	nx0	nx0	nx0
cp_rs2	x	x	x	x
cp_rd					x	x	x	x	x
cp_rs1_edges	x	x	x	x
cp_rs2_edges	x	x	x	x
cr_rs1_rs2_edges	offset	offset	offset	offset
cmp_rs1_rs2	x	x	x	x
cmp_rd_rs1						nx0	nx0	nx0	nx0
cp_offset	x	x	x	x		jalr
cp_imm_edges	branch	branch	branch	branch	jal	x	x	x	x
cp_gpr_hazard	r	r	r	r	w	rw	rw	rw	rw
cp_align							byte	byte
cp_memval							byte	byte	double

Instruction

bgeu

blt

bltu

bne

jal

jalr

lbu

Type

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_rs2_edges

offset

cmp_rs1_rs2

cmp_rd_rs1

nx0

cp_offset

jalr

cp_imm_edges

branch

jal

cp_gpr_hazard

cp_align

byte

cp_memval

byte

double

Instruction	lh	lhu	lui	lw	lwu	or	ori	sb	sd
Type	L	L	U	L	L	R	I	S	S
RV32	x	x	x	x		x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	nx0	nx0		nx0	nx0	x	x	nx0	nx0
cp_rs2						x		x	x
cp_rd	x	x	x	x	x	x	x
cp_rs1_edges						x	x
cp_rs2_edges						x		x	x
cr_rs1_imm_edges							x
cr_rs1_rs2_edges						x
cmp_rs1_rs2						x
cmp_rd_rs1	nx0	nx0		nx0	nx0	x	x
cmp_rd_rs2						x
cmp_rd_rs1_rs2						x
cp_imm_edges	x	x	20bit	x	x		x	x	x
cp_gpr_hazard	rw	rw	w	rw	rw	rw	rw	r	r
cp_align	hword	hword		word	word			byte
cp_memval	hword	hword		word	word

Instruction

lhu

lui

lwu

ori

Type

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_imm_edges

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

nx0

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_imm_edges

20bit

cp_gpr_hazard

cp_align

hword

word

byte

cp_memval

hword

word

Instruction	sh	sll	slli	slliw	sllw	slt	slti	sltiu	sltu
Type	S	R	IS	IS	R	R	I	I	R
RV32	x	x	x			x	x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	nx0	x	x	x	x	x	x	x	x
cp_rs2	x	x			x	x			x
cp_rd		x	x	x	x	x	x	x	x
cp_rs1_edges		x	x	x	x	x	x	x	x
cp_rs2_edges	x	x			x	x			x
cr_rs1_imm_edges			uimm	uimmw			x	x
cr_rs1_rs2_edges		x			x	x			x
cmp_rs1_rs2		x			x	x			x
cmp_rd_rs1		x	x	x	x	x	x	x	x
cmp_rd_rs2		x			x	x			x
cmp_rd_rs1_rs2		x			x	x			x
cp_uimm			x	5
cp_imm_edges	x						x	x
cp_gpr_hazard	r	rw	rw	rw	rw	rw	rw	rw	rw
cp_align	hword

Instruction

sll

slli

slliw

sllw

slt

slti

sltiu

sltu

Type

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_imm_edges

uimm

uimmw

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_uimm

cp_imm_edges

cp_gpr_hazard

cp_align

hword

Instruction	sra	srai	sraiw	sraw	srl	srli	srliw	srlw	sub
Type	R	IS	IS	R	R	IS	IS	R	R
RV32	x	x			x	x			x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x	x	x	x
cp_rs2	x			x	x			x	x
cp_rd	x	x	x	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x	x	x	x
cp_rs2_edges	x			x	x			x	x
cr_rs1_imm_edges		uimm	uimmw			uimm	uimmw
cr_rs1_rs2_edges	x			x	x			x	x
cmp_rs1_rs2	x			x	x			x	x
cmp_rd_rs1	x	x	x	x	x	x	x	x	x
cmp_rd_rs2	x			x	x			x	x
cmp_rd_rs1_rs2	x			x	x			x	x
cp_uimm		x	5			x	5
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	rw	rw	rw

Instruction

sra

srai

sraiw

sraw

srl

srli

srliw

srlw

sub

Type

RV32

RV64

cp_asm_count

cp_rs1

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_imm_edges

uimm

uimmw

uimm

uimmw

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_uimm

cp_gpr_hazard

Instruction	subw	sw	xor	xori	fence
Type	R	S	R	I	F
RV32		x	x	x	x
RV64	x	x	x	x	x
cp_asm_count	x	x	x	x	x
cp_rs1	x	nx0	x	x
cp_rs2	x	x	x
cp_rd	x		x	x
cp_rs1_edges	x		x	x
cp_rs2_edges	x	x	x
cr_rs1_imm_edges				x
cr_rs1_rs2_edges	x		x
cmp_rs1_rs2	x		x
cmp_rd_rs1	x		x	x
cmp_rd_rs2	x		x
cmp_rd_rs1_rs2	x		x
cp_imm_edges		x		x
cp_gpr_hazard	rw	r	rw	rw
cp_align		word
cp_custom					fence

Instruction

subw

xor

xori

fence

Type

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_imm_edges

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_imm_edges

cp_gpr_hazard

cp_align

word

cp_custom

fence

Table 11. I Modified Coverpoints
Modified Coverpoint	Bins	Definition
cp_rs1_nx0	31	The rs1 register number used in the instruction, excluding x0. x0 is hardwired to 0, which results in potentially access faults for loads, stores, and jalr.
cmp_rd_rs1_nx0	31	See cp_rs1_nx0
cp_offset_jalr	6	cp_offset + 2*2 combinations of rs1_val[0] and imm[0] affecting lsb of jalr address
cp_uimm_5	32	5-bit unsigned immediate shift amount for {slliw/srliw/sraiw}
cp_imm_edges_20bit	27	20-bit variant of Table 8 for `lui` and `auipc`.
cp_imm_edges_jal	23	20-bit positive and negative jump offsets for `jal`. Note that testing the full 20-bit range takes a large amount of program memory, so tests may cover a subset of this range.
cp_gpr_hazard_r	2	RAR and no hazard for instructions that only write a register
cp_gpr_hazard_w	3	WAW, WAR and no hazard for instructions that only write a register
cp_gpr_hazard_rw	4	RAW, WAW, WAR and no hazard for instructions that read and write registers
cp_align_{byte/hword/word}	8/4/2	Alignment of naturally-aligned load/store operand within doubleword in memory
cp_custom_fence	3	Test that fence, fence rw,rw, and fence.tso all execute without trapping.

Table 12 summarizes the normative rules in the RV{32/64}I specification and the unprivileged coverpoints that exercise them. Privileged coverpoints related to integer instructions are described in the relevent parts of Chapter 6. Note that the testplans always test the following fundamental capabilities, even if no normative rule is cited:

Opcodes (cp_asm_count)
All Source and Destination Registers (cp_rs1, cp_rs2, cp_rd)
Edge values (cp_rs1_edges, cp_rs2_edges, cp_imm_edges, cr_rs1_rs2_edges, cr_rs1_imm_edges)
All other bitfields in the instruction

Table 12. I Normative Rules
Unpriv Section	Normative Rule	Coverpoints
2.1	For RV32I, the 32 `x` registers are each 32 bits wide, i.e., `XLEN=32`.	cp_rs1, cp_rs2, cp_rd, cp_rs1_edges
2.1	Register `x0` is hardwired with all bits equal to 0.	cp_rs1, cp_rs2, cp_rd
2.2	In the base RV32I ISA, there are four core instruction formats (R/I/S/U)	cp_asm_count
2.2	Except for the 5-bit immediates used in CSR instructions (Chapter 6), immediates are always sign-extended	cp_imm_edges
2.2	Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced.	cp_imm_edges
2.3	The only difference between the S and B formats is that the 12-bit immediate field is used to encode branch offsets in multiples of 2 in the B format. Instead of shifting all bits in the instruction-encoded immediate left by one in hardware as is conventionally done, the middle bits (imm[10:1]) and sign bit stay in fixed positions, while the lowest bit in S format (inst[7]) encodes a high-order bit in B format.	{store/branch}/cp_imm_edges
2.3	[T]he only difference between the U and J formats is that the 20-bit immediate is shifted left by 12 bits to form U immediates and by 1 bit to form J immediates. The location of instruction bits in the U and J format immediates is chosen to maximize overlap with the other formats and with each other.	{lui/jalr}/cp_imm_edges
2.3	Sign extensions always uses inst[31].	cp_imm_edges
2.4	Most integer computational instructions operate on XLEN bits of values held in the integer register file.	cp_rs1, cp_rs2, cr_rs1_rs2_edges
2.4	Integer computational instructions are either encoded as register-immediate operations using the I-type format or as register-register operations using the R-type format.	cp_rs1, cp_cp_rs1_imm_edges
2.4	The destination is register rd for both register-immediate and register-register instructions.	cp_rd
2.4	No integer computational instructions cause arithmetic exceptions.	No such exceptions exist, so nothing to test.
2.4.1	ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and the result is simply the low XLEN bits of the result.	addi/cp_rs1_imm_edges
2.4.1	SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd.	slti/cp_rs1_imm_edges
2.4.1	SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number).	sltiu/cp_rs1_imm_edges
2.4.1	ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.	{andi/ori/xori}/cp_rs1_imm_edges
2.4.1	Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field. The right shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).	{slli/srli/srai}/cp_rs1_imm_edges, cp_uimm
2.4.1	LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the 32-bit U-immediate value into the destination register rd, filling in the lowest 12 bits with zeros.	lui/cp_imm_edges_20bit, cp_rd
2.4.1	AUIPC (add upper immediate to `pc`) is used to build `pc`-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, adds this offset to the address of the AUIPC instruction, then places the result in register rd.	auipc/cp_imm_edges_20bit, cp_rd
2.4.2	RV32I defines several arithmetic R-type operations. All operations read the rs1 and rs2 registers as source operands and write the result into register rd. The funct7 and funct3 fields select the type of operation.	cr_rs1_rs2_edges, cp_rs1, cp_rs2, cp_rd
2.4.2	ADD performs the addition of rs1 and rs2.	add/cp_rs1_rs2_edges
2.4.2	SUB performs the subtraction of rs2 from rs1. Overflows are ignored and the low XLEN bits of results are written to the destination rd.	sub/cp_rs1_rs2_edges
2.4.2	SLT and SLTU perform signed and unsigned compares respectively, writing 1 to rd if rs1 < rs2, 0 otherwise.	{slt/sltu}/cp_rs1_rs2_edges
2.4.2	AND, OR, and XOR perform bitwise logical operations.	{and/or/xor}/cp_rs1_rs2_edges
2.4.2	SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.	{sll/srl/sra}/cp_rs1_rs2_edges, cp_rs2
2.4.3	The NOP instruction does not change any architecturally visible state, except for advancing the `pc` and incrementing any applicable performance counters. NOP is encoded as ADDI x0, x0, 0.	addi/cp_rs1_imm_edges
2.5.1	The jump and link (JAL) instruction uses the J-type format, where the J-immediate encodes a signed offset in multiples of 2 bytes. The offset is sign-extended and added to the address of the jump instruction to form the jump target address.	jal/cp_imm_edges_jal
2.5.1	Plain unconditional jumps (assembler pseudoinstruction J) are encoded as a JAL with rd=`x0`.	jal/cp_rd
2.5.1	The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting the least-significant bit of the result to zero. The address of the instruction following the jump (`pc`+4) is written to register rd. Register `x0` can be used as the destination if the result is not required.	jalr/{cp_offset_jalr, cp_rd, cp_imm_edges}
2.5.2	All branch instructions use the B-type instruction format. The 12-bit B-immediate encodes signed offsets in multiples of 2 bytes. The offset is sign-extended and added to the address of the branch instruction to give the target address.	{beq/bne/blt/bge/bltu/bgeu}/cp_imm_edges_branch
2.5.2	BEQ and BNE take the branch if registers rs1 and rs2 are equal or unequal respectively.	{beq/bne}/cr_rs1_rs2_edges_offset
2.5.2	BLT and BLTU take the branch if rs1 is less than rs2, using signed and unsigned comparison respectively.	{blt/bltu}/cr_rs1_rs2_edges_offset
2.5.2	BGE and BGEU take the branch if rs1 is greater than or equal to rs2, using signed and unsigned comparison respectively.	{bge/bgeu}/cr_rs1_rs2_edges_offset
2.6	The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.	cp_imm_edges
2.6	Loads copy a value from memory to register rd.	{lb/lbu/lh/lhu/lw}/{cp_rd}
2.6	Stores copy the value in register rs2 to memory.	{sb/sh/sw}/{cp_rs2}
2.6	The LW instruction loads a 32-bit value from memory into rd.	{cp_rd}
2.6	LH loads a 16-bit value from memory, then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.	{lh/lhu/lb/lbu}/{cp_rd} hits these with random values. 32 random values is sufficient to ensure sign and zero extension are taking place.
2.6	The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory.	{sw/sh/sb}/cp_rs2_edges
2.6	loads and stores whose effective addresses are naturally aligned shall not raise an address-misaligned exception.	untestable
2.7	FENCE instructions are used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors.	fence/cp_asm_count; behavior untestable from a single core
2.9	Implementations are always allowed to ignore the encoded hints.	Untested because they may not be implemented.
RV64-Specific Statements
4.1	RV64I widens the integer registers and supported user address space to 64 bits	cp_rs1, cp_rs2, cp_rs1_rs2_edges
4.2.1	ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1 and produces the proper sign extension of a 32-bit result in rd. Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits.	cp_rs1_imm_edges
4.2.1	Shifts by a constant are encoded as a specialization of the I-type format using the same instruction opcode as RV32I. The operand to be shifted is in rs1, and the shift amount is encoded in the lower 6 bits of the I-immediate field for RV64I. The right shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).	{slli/srli/srai}/cp_rs1_imm_edges, cp_uimm
4.2.1	SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits.	{slliw/srliw/sraiw}/cp_rs1_imm_edges, cp_uimm
4.2.1	LUI (load upper immediate) uses the same opcode as RV32I. LUI places the 32-bit U-immediate into register rd, filling in the lowest 12 bits with zeros. The 32-bit result is sign-extended to 64 bits.	lui/cp_imm_edges_20bit, cp_rd
4.2.1	AUIPC (add upper immediate to `pc`) uses the same opcode as RV32I. AUIPC is used to build `pc`-relative addresses and uses the U-type format. AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest 12 bits with zeros, sign-extends the result to 64 bits, adds it to the address of the AUIPC instruction, then places the result in register rd.	auipc/cp_imm_edges_20bit, cp_rd
4.2.2	ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low 32-bits of the result is sign-extended to 64-bits and written to the destination register.	{addw/subw}/cp_rs1_rs2_edges
4.2.2	SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in register rs2. In RV64I, only the low 6 bits of rs2 are considered for the shift amount.	{sll/srl/sra}/cp_rs1_rs2_edges
4.2.2	SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate on 32-bit values and sign-extend their 32-bit results to 64 bits. The shift amount is given by rs2[4:0].	{sllw/srlw/sraw}/cp_rs1_rs2_edges, cp_rs2
4.3	RV64I extends the address space to 64 bits. The execution environment will define what portions of the address space are legal to access.	untestable
4.3	The LD instruction loads a 64-bit value from memory into register rd for RV64I.	ld/cp_rd
4.3	The LW instruction loads a 32-bit value from memory and sign-extends this to 64 bits before storing it in register rd for RV64I. The LWU instruction, on the other hand, zero-extends the 32-bit value from memory for RV64I. LH and LHU are defined analogously for 16-bit values, as are LB and LBU for 8-bit values.	lb/cp_memval_byte, lbu/cp_memval_byte, lh/cp_memval_half, lhu/cp_memval_half, lw/cp_memval_word, lwu/cp_memval_word
4.3	The SD, SW, SH, and SB instructions store 64-bit, 32-bit, 16-bit, and 8-bit values from the low bits of register rs2 to memory respectively.	{sd/sw/sh/sb}/cp_rs2_edges
4.4	The additional computational instructions in RV64I expand both the standard and custom HINT encoding spaces.	untestable

Table 13. I Reserved Behavior
Unpriv Section	Normative Rule	Coverpoints
4.2.1	SLLIW, SRLIW, and SRAIW encodings with imm[5] ≠ 0 are reserved.	cp_uimm_5. See also Ssstrict in Section 6.8

5.4. M Multiply Extension

Table 14 summarizes the coverpoints for the M extension. Table 15 summarizes the relevant normative rules.

Table 14. M Instruction Coverpoints
Instruction	div	divu	divuw	divw	mul	mulh	mulhsu	mulhu	mulw
Type	R	R	R	R	R	R	R	R	R
RV32	x	x			x	x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x	x	x	x
cp_rs2	x	x	x	x	x	x	x	x	x
cp_rd	x	x	x	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x	x	x	x
cp_rs2_edges	x	x	x	x	x	x	x	x	x
cr_rs1_rs2_edges	x	x	x	x	x	x	x	x	x
cmp_rs1_rs2	x	x	x	x	x	x	x	x	x
cmp_rd_rs1	x	x	x	x	x	x	x	x	x
cmp_rd_rs2	x	x	x	x	x	x	x	x	x
cmp_rd_rs1_rs2	x	x	x	x	x	x	x	x	x
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	rw	rw	rw

Instruction	rem	remu	remuw	remw
Type	R	R	R	R
RV32	x	x
RV64	x	x	x	x
cp_asm_count	x	x	x	x
cp_rs1	x	x	x	x
cp_rs2	x	x	x	x
cp_rd	x	x	x	x
cp_rs1_edges	x	x	x	x
cp_rs2_edges	x	x	x	x
cr_rs1_rs2_edges	x	x	x	x
cmp_rs1_rs2	x	x	x	x
cmp_rd_rs1	x	x	x	x
cmp_rd_rs2	x	x	x	x
cmp_rd_rs1_rs2	x	x	x	x
cp_gpr_hazard	rw	rw	rw	rw

Instruction

rem

remu

remuw

remw

Type

RV32

RV64

cp_asm_count

cp_rs1

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_gpr_hazard

Table 15. M Normative Rules
Unpriv Section	Normative Rule	Coverpoints
12.1	MUL performs an XLEN-bit×XLEN-bit multiplication of `rs1` by `rs2` and places the lower XLEN bits in the destination register.	mul/{cp_rs1, cp_rs2, cp_rd, cr_rs1_rs2_edges}
12.1	MULH, MULHU, and MULHSU perform the same multiplication but return the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned, and `rs1`×unsigned `rs2` multiplication.	{mulh/mulhu/mulhsu}/cr_rs1_rs2_edges
12.1	MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the sign extension of the lower 32 bits of the result into the destination register.	mulw/cr_rs1_rs2_edges
12.2	DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of `rs1` by `rs2`, rounding towards zero.	{div/divu}/cr_rs1_rs2_edges
12.2	REM and REMU provide the remainder of the corresponding division operation. For REM, the sign of a nonzero result equals the sign of the dividend.	{rem/remu}/cr_rs1_rs2_edges
12.2	DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of `rs1` by the lower 32 bits of `rs2`, treating them as signed and unsigned integers, placing the 32-bit quotient in `rd`, sign-extended to 64 bits.	{divw/divuw}/cr_rs1_rs2_edges
12.2	REMW and REMUW are RV64 instructions that provide the corresponding signed and unsigned remainder operations. Both REMW and REMUW always sign-extend the 32-bit result to 64 bits, including on a divide by zero.	{remw/remuw}/cr_rs1_rs2_edges
12.2	The semantics for division by zero and division overflow are summarized in [divby0]. The quotient of division by zero has all bits set, and the remainder of division by zero equals the dividend. Signed division overflow occurs only when the most-negative integer is divided by . The quotient of a signed division with overflow is equal to the dividend, and the remainder is zero. Unsigned division overflow cannot occur.	cp_rs1_rs2_edges

5.4.1. Zmmul

The Zmmul extension is a subset of the M extension that includes only the multiply instructions. The coverpoints are listed in Table 16.

Table 16. Zmmul Instruction Coverpoints
Instruction	mul	mulh	mulhsu	mulhu	mulw
Type	R	R	R	R	R
RV32	x	x	x	x
RV64	x	x	x	x	x
cp_asm_count	x	x	x	x	x
cp_rs1	x	x	x	x	x
cp_rs2	x	x	x	x	x
cp_rd	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x
cp_rs2_edges	x	x	x	x	x
cr_rs1_rs2_edges	x	x	x	x	x
cmp_rs1_rs2	x	x	x	x	x
cmp_rd_rs1	x	x	x	x	x
cmp_rd_rs2	x	x	x	x	x
cmp_rd_rs1_rs2	x	x	x	x	x
cp_gpr_hazard	rw	rw	rw	rw	rw

Table 17. Zmmul Normative Rules
Unpriv Section	Normative Rule	Coverpoints
12.3	The `Zmmul` extension implements the multiplication subset of the M extension. It adds all of the instructions defined in [Multiplication Operations], namely: MUL, MULH, MULHU, MULHSU, and (for RV64 only) MULW. The encodings are identical to those of the corresponding M-extension instructions.	{mul/mulh/mulhu/mulhsu/mulw}/cr_rs1_rs2_edges

5.5. C Compressed Extension

The C extension is subdivided into Zca, Zcf, and Zcd. All configurations supporting C contain Zca. RV32CF configurations also contain Zcf, and RV{32/64}CD configurations also contain Zcd. A configuration supporting C should test all of the applicable Zc* extensions. Table 18 lists the normative rules in the RV{32/64}C specification applicable to all instructions, and the unprivileged coverpoints that exercise them.

Table 18. C Normative Rules
Unpriv Section	Normative Rule	Coverpoints
27.1	The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary, i.e., IALIGN=16.	*
27.1	The compressed instruction encodings are mostly common across RV32C and RV64C, but as shown in Table 34, a few opcodes are used for different purposes depending on base ISA.	Run relevant test suites. ***drop
27.1	If the C extension is implemented, the appropriate compressed floating-point load and store instructions must be provided whenever the relevant standard floating- point extension (F and/or D) is also implemented.	Run relevant test suites. ***drop
27.2	CR, CI, and CSS can use any of the 32 RVI registers, but CIW, CL, CS, CA, and CB are limited to just 8 of them.	cp_rs1p, cp_rs2p, cp_rdp
27.2	Compressed register-based floating-point loads and stores also use the CL and CS formats respectively, with the eight registers mapping to `f8` to `f15`.	cp_fdp, cp_fs2p
27.2	For many RVC instructions, zero-valued immediates are disallowed and `x0` is not a valid 5-bit register specifier.	cp_rs1_imm_edges,cp_imm_mul, _nx0 coverpoints
27.4	As with base RVI instructions, the offsets of all RVC control transfer instructions are in multiples of 2 bytes.	*
27.7	A portion of the RVC encoding space is reserved for microarchitectural HINTs. …these instructions do not modify any architectural state, except for advancing the `pc` and any applicable performance counters. HINTs are executed as no-ops on implementations that ignore them.	Hints are not tested

Table 97 summarizes normative rules relating to compressed instructions affecting privileged behavior.

5.5.1. Zca Compressed Extension

Table 19 summarizes the coverpoints for the Zca extension.

Table 19. Zca Instruction Coverpoints
Instruction	c.add	c.addi	c.addi16sp	c.addi4spn	c.addiw	c.addw	c.and	c.andi	c.beqz
Type	CR	CI	CI	CIW	CI	CA	CA	CBP	CB
RV32	x	x	x	x			x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs2	nx0
cp_rd	nx0	nx0			nx0
cp_rs1_edges	x	x			x	x	x	x	x
cp_rs2_edges	x					x	x
cr_rs1_imm_edges		6bit_n0			6bit			6bit
cr_rs1_rs2_edges	x
cmp_rs1_rs2						c	c
cmp_rd_rs1								c
cmp_rd_rs2	nx0					c	c
cp_offset									x
cp_rs1p									x
cp_rs2p						x	x
cp_rdp				x		x	x	x
cp_imm_mul			addi16sp	addi4spn

Instruction	c.bnez	c.j	c.jal	c.jalr	c.jr	c.ld	c.ldsp	c.li	c.lui
Type	CB	CJ	CJAL	CJALR	CJR	CL	CI	CI	CI
RV32	x	x	x	x	x			x	x
RV64	x	x		x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1				nx0	nx0
cp_rd							nx0	nx0	nx2
cp_rs1_edges	x
cmp_rd_rs1						c
cp_offset	x	x	x	c_jr	c_jr
cp_imm_edges		c_jal	c_jal					6bit	6bit_n0
cp_rs1p	x					x
cp_rdp						x
cp_imm_mul						8	8sp

Instruction

c.bnez

c.j

c.jal

c.jalr

c.jr

c.ld

c.ldsp

c.li

c.lui

Type

CJAL

CJALR

CJR

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rd

nx0

nx2

cp_rs1_edges

cmp_rd_rs1

cp_offset

c_jr

cp_imm_edges

c_jal

6bit

6bit_n0

cp_rs1p

cp_rdp

cp_imm_mul

8sp

Instruction

c.lw

c.lwsp

c.mv

c.nop

c.or

c.sd

c.sdsp

c.slli

c.srai

Type

CLS

CSS

CBP

RV32

RV64

cp_asm_count

cp_rs2

nx0

cp_rd

nx0

cp_rs1_edges

cp_rs2_edges

cr_rs1_imm_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

nx0

cp_uimm

cp_rs1p

cp_rs2p

cp_rdp

cp_imm_mul

4sp

8sp

Instruction	c.srli	c.sub	c.subw	c.sw	c.swsp	c.xor
Type	CBP	CA	CA	CS	CSS	CA
RV32	x	x		x	x	x
RV64	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x
cp_rs2					x
cp_rs1_edges	x	x	x			x
cp_rs2_edges		x	x	x	x	x
cr_rs1_imm_edges	c
cmp_rs1_rs2		c	c			c
cmp_rd_rs1	c
cmp_rd_rs2		c	c			c
cp_uimm	n0
cp_rs1p				x
cp_rs2p		x	x	x		x
cp_rdp	x	x	x			x
cp_imm_mul				x	4sp

Instruction

c.srli

c.sub

c.subw

c.sw

c.swsp

c.xor

Type

CBP

CSS

RV32

RV64

cp_asm_count

cp_rs2

cp_rs1_edges

cp_rs2_edges

cr_rs1_imm_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cp_uimm

cp_rs1p

cp_rs2p

cp_rdp

cp_imm_mul

4sp

Table 20. Zca Normative Rules
Unpriv Section	Normative Rule	Coverpoints
27.3.1	C.LWSP loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to lw rd, offset(x2). C.LWSP is valid only when rd≠x0; the code points with rd=x0 are reserved.	c.lwsp/{cp_imm_mul_4sp, rd_nx0}
27.3.1	C.LDSP is an RV64C-only instruction that loads a 64-bit value from memory into register rd. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to ld rd, offset(x2). C.LDSP is valid only when rd≠x0; the code points with rd=x0 are reserved.	c.ldsp/{cp_imm_mul_8sp, rd_nx0}
27.3.1	C.SWSP stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to sw rs2, offset(x2).	c.swsp/{imm_mul_4sp, cp_rs2_edges}
27.3.1	C.SDSP is an RV64C-only instruction that stores a 64-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to sd rs2, offset(x2).	c.sdsp/{imm_mul_8sp, cp_rs2_edges}
27.3.2	C.LW loads a 32-bit value from memory into register `rd′`. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`. It expands to `lw rd′, offset(rs1′)`.	c.lw/{cp_imm_mul, cp_rs1p, cp_rdp}
27.3.2	C.LD is an RV64C-only instruction that loads a 64-bit value from memory into register `rd′`. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`. It expands to `ld rd′, offset(rs1′)`.	c.ld/{cp_imm_mul_8, cp_rs1p, cp_rdp}
27.3.2	C.SW stores a 32-bit value in register rs2′ to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1′. It expands to sw rs2′, offset(rs1′).	c.sw/{cp_imm_mul, cp_rs1p, cp_rs2_edges}
27.3.2	C.SD is an RV64C-only instruction that stores a 64-bit value in register `rs2′` to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`. It expands to `sd rs2′, offset(rs1′)`.	c.sd/{cp_imm_mul_8, cp_rs1p, cp_rs2_edges}
27.4	C.J performs an unconditional control transfer. The offset is sign-extended and added to the `pc` to form the jump target address. C.J can therefore target a ±2 KiB range. C.J expands to `jal x0, offset`.	c.j/{cp_imm_edges_c_jal}
27.4	C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (`pc+2`) to the link register, `x1`. C.JAL expands to `jal x1, offset`.	c.jal/{cp_imm_edges_c_jal}
27.4	C.JR (jump register) performs an unconditional control transfer to the address in register rs1. C.JR expands to `jalr x0, 0(rs1)`. C.JR is valid only when rs1≠`x0`; the code point with rs1=`x0` is reserved.	c.jr/{cp_rs1_nx0}
27.4	C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (`pc`+2) to the link register, `x1`. C.JALR expands to `jalr x1, 0(rs1)`. C.JALR is valid only when rs1≠`x0`; the code point with rs1=`x0` corresponds to the C.EBREAK instruction.	c.jalr/{cp_rs1_nx0}, ExceptionsZc/cp_breakpoint
27.4	C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the `pc` to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1′ is zero. It expands to `beq rs1′, x0, offset`.	c.beqz/{cp_offset, cp_rs1_edges}
27.4	C.BNEZ is defined analogously, but it takes the branch if rs1′ contains a nonzero value. It expands to `bne rs1′, x0, offset`.	c.bnez/{cp_offset, cp_rs1_edges}
27.5.1	C.LI loads the sign-extended 6-bit immediate, imm, into register rd. C.LI expands into `addi rd, x0, imm`. The C.LI code points with rd=`x0` are HINTs.	c.li/{cp_imm_edges_6bit, cp_rd_nx0}
27.5.1	C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into `lui rd, imm`. C.LUI is valid only when rd≠`x2`, and when the immediate is not equal to zero. The code points with imm=0 are reserved.	c.lui/{cp_imm_edges_6bit, cp_rd_nx2}
27.5.2	C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into addi rd, rd, imm. C.ADDI is valid only when rd≠x0 and imm≠0.	c.addi/{cr_rs1_imm_edges_6bit_n0, cp_rd_nx0}
27.5.2	C.ADDIW is an RV64C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into `addiw rd, rd, imm`. The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`.	c.addiw/{cr_rs1_imm_edges_6bit, cp_rd_nx0}
27.5.2	C.ADDI16SP (add immediate to stack pointer) shares the opcode with C.LUI, but has a destination field of `x2`. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (`sp=x2`), where the immediate is scaled to represent multiples of 16 in the range [-512, 496]. C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. It expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is valid only when nzimm≠0; the code point with nzimm=0 is reserved.	c.addi16sp/{cp_imm_mul_addi16sp}
27.5.2	C.ADDI4SPN (add immediate to stack pointer, non-destructive) is a CIW-format instruction that adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, `x2`, and writes the result to `rd′`. This instruction is used to generate pointers to stack-allocated variables, and expands to `addi rd′, x2, nzuimm[9:2]`. C.ADDI4SPN is valid only when nzuimm≠0; the code points with nzuimm=0 are reserved.	c.addi4spn/{cp_imm_mul_addi4spn, cp_rdp}
27.5.2	C.SLLI is a CI-format instruction that performs a logical left shift of the value in register rd then writes the result to rd. The shift amount is encoded in the shamt field. C.SLLI expands into `slli rd, rd, shamt[5:0]`.	c.slli/{cr_rs1_imm_edges_c}
27.5.2	The C.SLLI code points with shamt=0 or with rd=`x0` are HINTs.	c.slli/{cp_rd_nx0, cr_rs1_imm_edges_c}
27.5.2	C.SRLI is a CB-format instruction that performs a logical right shift of the value in register rd′ then writes the result to rd′. The shift amount is encoded in the shamt field. C.SRLI expands into `srli rd′, rd′, shamt`.	c.srli/{ cr_rs1_imm_edges_c, cp_rdp}
27.5.2	C.SRAI is defined analogously to C.SRLI, but instead performs an arithmetic right shift. C.SRAI expands to `srai rd′, rd′, shamt`.	c.srai/{cr_rs1_imm_edges_c, cp_rdp}
27.5.2	For RV32C, shamt[5] must be zero; the code points with shamt[5]=1 are designated for custom extensions.	c.{slli,srli, srai}/{cr_rs1_imm_edges_c}
27.5.2	C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register rd′ and the sign-extended 6-bit immediate, then writes the result to rd′. C.ANDI expands to `andi rd′, rd′, imm`.	c.andi/{cr_rs1_imm_edges_6bit, cp_rdp}
27.5.3	C.MV copies the value in register rs2 into register rd. C.MV expands into `add rd, x0, rs2`. C.MV is valid only when rs2≠`x0`	c.mv/{cp_rd_nx0, cp_rs2_nx0}
27.5.3	C.ADD adds the values in registers rd and rs2 and writes the result to register rd. C.ADD expands into `add rd, rd, rs2`. C.ADD is only valid when rs2≠`x0`	c.add/{cp_rs1_rs2_edges, cp_rs2_nx0, cp_rd_nx0}
27.5.3	`C.AND` computes the bitwise `AND` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.AND` expands into `and rd′, rd′, rs2′`.	c.and/{cp_rdp, cp_rs2p}
27.5.3	`C.OR` computes the bitwise `OR` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.OR` expands into `or rd′, rd′, rs2′`.	c.or/{cp_rdp, cp_rs2p}
27.5.3	`C.XOR` computes the bitwise `XOR` of the values in registers rd′ and rs2′, then writes the result to register rd′. `C.XOR` expands into `xor rd′, rd′, rs2′`.	c.xor/{cp_rdp, cp_rs2p}
27.5.3	`C.SUB` subtracts the value in register rs2′ from the value in register rd′, then writes the result to register rd′. `C.SUB` expands into `sub rd′, rd′, rs2′`.	c.sub/{cp_rdp, cp_rs2p}
27.5.3	`C.ADDW` is an RV64C-only instruction that adds the values in registers rd′ and rs2′, then sign-extends the lower 32 bits of the sum before writing the result to register rd′. `C.ADDW` expands into `addw rd′, rd′, rs2′`.	c.addw/{cp_rdp, cp_rs2p}
27.5.3	`C.SUBW` is an RV64C-only instruction that subtracts the value in register rs2′ from the value in register rd′, then sign-extends the lower 32 bits of the difference before writing the result to register rd′. `C.SUBW` expands into `subw rd′, rd′, rs2′`.	c.subw/{cp_rdp, cp_rs2p}
27.5.6	`C.NOP` is a CI-format instruction that does not change any user-visible state, except for advancing the `pc` and incrementing any applicable performance counters. `C.NOP` expands to `nop`.	c.nop/{cp_asm_count}

5.5.2. Zcf Compressed Floating-Point Extension

Table 21 summarizes the coverpoints for the Zcf extension.

Table 21. Zcf Instruction Coverpoints
Instruction	c.flw	c.flwsp	c.fsw	c.fswsp
Type	CFL	CFLS	CFS	CFSS
RV32	x	x	x	x
cp_asm_count	x	x	x	x
cp_rs1p	x		x
cp_fdp	x
cp_fs2p			x
cp_imm_mul	x	4sp	x	4sp
cp_fs2				x
cp_fd		x

Table 22. Zcf Normative Rules
Unpriv Section	Normative Rule	Coverpoints
27.3.1	C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to flw rd, offset(x2).	c.flwsp/*
27.3.1	C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating- point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. It expands to fsw rs2, offset(x2).	c.fswsp/*
27.3.2	C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register `rd′`. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`. It expands to `flw rd′, offset(rs1′)`.	c.flw/{}
27.3.2	C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register `rs2′` to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register `rs1′`. It expands to `fsw rs2′, offset(rs1′)`.	c.fsw/{}

5.5.3. Zcd Compressed Double-Precision FP Extension

Table 23 summarizes the coverpoints for the Zcd extension.

Table 23. Zcd Instruction Coverpoints
Instruction	c.fld	c.fldsp	c.fsd	c.fsdsp
Type	CFL	CFLS	CFS	CFSS
RV32	x	x	x	x
RV64	x	x	x	x
cp_asm_count	x	x	x	x
cp_rs1p	x		x
cp_fdp	x
cp_fs2p			x
cp_imm_mul	8	8sp	8	8sp
cp_fs2				x
cp_fd		x

Table 24. Zcd Normative Rules
Unpriv Section	Normative Rule	Coverpoints
27.3.1	C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register rd. It computes its effective address by adding the zero -extended offset, scaled by 8, to the stack pointer, x2. It expands to fld rd, offset(x2).	c.fldsp/*
27.3.1	C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, x2. It expands to fsd rs2, offset(x2).	c.fsdsp/*
27.3.2	C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register `rd′`. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`. It expands to `fld rd′, offset(rs1′)`.	c.fld/{}
27.3.2	C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register `rs2′` to memory. It computes an effective address by adding the zero-extended offset, scaled by 8, to the base address in register `rs1′`. It expands to `fsd rs2′, offset(rs1′)`.	c.fsd/{}

5.5.4. Zcb Additional Compressed Instructions

Table 25 summarizes the coverpoints for the Zcb extension.

Table 25. Zcb Instruction Coverpoints
Instruction	c.lbu	c.lh	c.lhu	c.not	c.sb	c.sh	c.zext.b
Type	CLB	CLH	CLH	CU	CSB	CSH	CU
RV32	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x
cp_rs1_edges				x			x
cp_rs2_edges					x	x
cmp_rd_rs1	c	c	c
cp_rs1p	x	x	x	x	x	x	x
cp_rs2p					x	x
cp_rdp	x	x	x	x			x

Table 26. Zcb Normative Rules
Unpriv Section	Normative Rule	Coverpoints
28.12.1	c.lbu loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended to XLEN bits and is written to rd'.	c.lbu/{}
28.12.2	c.lhu loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended to XLEN bits and is written to rd'.	c.lhu/{}
28.12.3	c.lh loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended to XLEN bits and is written to rd'.	c.lh/{}
28.12.4	c.sb stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.	c.sb/{}
28.12.5	c.sh stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.	c.sh/{}
28.12.6	c.zext.b takes a single source/destination operand. It zero-extends the least-significant byte of the operand to XLEN bits by inserting zeros into all of the bits more significant than 7.	c.zext.b/{}
28.12.11	c.not takes the one’s complement of rd'/rs1' and writes the result to the same register.	c.not/{}

5.5.4.1. ZcbM

When both Zcb and M are supported, add the instruction in Table 27 to the Zcb coverpoints.

Table 27. ZcbM Instruction Coverpoints
Instruction	c.mul
Type	CA
RV32	x
RV64	x
cp_asm_count	x
cmp_rd_rs2	c
cp_rs2p	x
cp_rdp	x

Table 28. ZcbM Normative Rules
Unpriv Section	Normative Rule	Coverpoints
28.12.12	c.mul multiplies XLEN bits of the source operands from rsd' and rs2' and writes the lowest XLEN bits of the result to rsd'.	c.mul/{}

5.5.4.2. ZcbZba

When both Zcb and Zba are supported, add the instruction in Table 29 to the Zcb coverpoints.

Table 29. ZcbZba Instruction Coverpoints
Instruction	c.zext.w
Type	CU
RV64	x
cp_asm_count	x
cp_rs1_edges	x
cp_rs1p	x
cp_rdp	x

Table 30. ZcbZba Normative Rules
Unpriv Section	Normative Rule	Coverpoints
28.12.10	c.zext.w takes a single source/destination operand. It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.	c.zext.w/{}

5.5.4.3. ZcbZbb

When both Zcb and Zbb are supported, add the instructions in Table 31 to the Zcb coverpoints.

Table 31. ZcbZbb Instruction Coverpoints
Instruction	c.sext.b	c.sext.h	c.zext.h
Type	CU	CU	CU
RV32	x	x	x
RV64	x	x	x
cp_asm_count	x	x	x
cp_rs1_edges	x	x	x
cp_rs1p	x	x	x
cp_rdp	x	x	x

Table 32. ZcbZbb Normative Rules
Unpriv Section	Normative Rule	Coverpoints
28.12.7	c.sext.b takes a single source/destination operand. It sign-extends the least-significant byte in the operand to XLEN bits by copying the most-significant bit in the byte (i.e., bit 7) to all of the more- significant bits.	c.sext.b/{}
28.12.8	c.zext.h takes a single source/destination operand. It zero-extends the least-significant halfword of the operand to XLEN bits by inserting zeros into all of the bits more significant than 15.	c.zext.h/{}
28.12.9	c.sext.h takes a single source/destination operand. It sign-extends the least-significant halfword in the operand to XLEN bits by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.	c.sext.h/{}

5.6. A Atomic Extension

The A extension is subdivided into Zaamo and Zalrsc. Table 33 lists the normative rules in the RV{32/64}A specification applicable to all instructions, and the unprivileged coverpoints that exercise them.

Table 33. A Normative Rules
Unpriv Section	Normative Rule	Coverpoints

[t-A-priv-normative-rules] summarizes normative rules relating to atomic instructions affecting privileged behavior.

5.6.1. Zaamo Atomic Memory Operations Extension

Table 34 summarizes the coverpoints for the Zaamo extension.

Table 34. Zaamo Instruction Coverpoints
Instruction	amoadd.d	amoadd.w	amoand.d	amoand.w	amomax.d	amomax.w	amomaxu.d	amomaxu.w	amomin.d
Type	A	A	A	A	A	A	A	A	A
RV32		x		x		x		x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0
cp_rs2	x	x	x	x	x	x	x	x	x
cp_rd	x	x	x	x	x	x	x	x	x
cp_rs2_edges	x	x	x	x	x	x	x	x	x
cmp_rs1_rs2	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0
cmp_rd_rs1	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0
cmp_rd_rs2	x	x	x	x	x	x	x	x	x
cmp_rd_rs1_rs2	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	rw	rw	rw
cp_align		word		word		word		word

Instruction

amomin.w

amominu.d

amominu.w

amoor.d

amoor.w

amoswap.d

amoswap.w

amoxor.d

amoxor.w

Type

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rs2

cp_rd

cp_rs2_edges

cmp_rs1_rs2

nx0

cmp_rd_rs1

nx0

cmp_rd_rs2

cmp_rd_rs1_rs2

nx0

cp_gpr_hazard

cp_align

word

5.6.2. Zalrsc Load-Reserved / Store-Conditional Extension

Table 36 summarizes the coverpoints for the Zalrsc extension.

Table 36. Zalrsc Instruction Coverpoints
Instruction	lr.d	lr.w	sc.d	sc.w
Type	I1	I1	SC	SC
RV32		x		x
RV64	x	x	x	x
cp_asm_count	x	x	x	x
cp_rs1	nx0	nx0	nx0	nx0
cp_rs2			x	x
cp_rd	x	x	x	x
cp_rs2_edges			x	x
cmp_rs1_rs2			nx0	nx0
cmp_rd_rs1	nx0	nx0	nx0	nx0
cmp_rd_rs2			x	x
cmp_rd_rs1_rs2			nx0	nx0
cp_sc			x	x
cp_gpr_hazard	rw	rw	rw	rw
cp_custom	lr	lr	sc	sc

On implementations that support the C extension, compressed forms of the I instructions permitted inside constrained LR/SC sequences, as described in [sec:lrscseq], are also perm

5.7. Floating-Point Extensions

Supporting floating-point involves enabling at least the F extension. Other extensions depend on F. The coverpoints are specified in the following sections. Some tests only apply when multiple extensions are supported.

5.7.1. F Single-Precision FP

Table 38. F Instruction Coverpoints
Instruction	fadd.s	fclass.s	fcvt.l.s	fcvt.lu.s	fcvt.s.l	fcvt.s.lu	fcvt.s.w	fcvt.s.wu	fcvt.w.s
Type	FR	FIX	F2X	F2X	X2F	X2F	X2F	X2F	F2X
RV32	x	x					x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1					x	x	x	x
cp_rd		x	x	x					x
cp_rs1_edges					x	x	x	x
cp_fs1	x	x	x	x					x
cp_fs2	x
cp_fd	x				x	x	x	x
cp_fs1_edges	x	x	frm	frm					frm
cp_fs2_edges	x
cmp_fd_fs1	x
cmp_fd_fs2	x
cp_frm	3		2	2	2	2	2	2	2
cp_csr_fflags	von		vn	vn	n	n	n	n	vn
cp_csr_frm	x		x	x	x	x	x	x	x
cr_fs1_fs2_edges	frm
cp_fclass		x
cp_fpr_hazard	rw	r	r	r	w	w	w	w	r
cp_gpr_hazard		w	w	w	r	r	r	r	w

Instruction

fcvt.wu.s

fdiv.s

feq.s

fle.s

flt.s

flw

fmadd.s

fmax.s

fmin.s

Type

F2X

FR4

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rd

cp_imm_edges

cp_fs1

cp_fs2

cp_fs3

cp_fd

cp_fs1_edges

frm

cp_fs2_edges

cp_fs3_edges

cmp_fd_fs1

cmp_fd_fs2

cmp_fd_fs3

cp_frm

cp_csr_fflags

vdoun

voun

cp_csr_frm

cr_fs1_fs2_edges

frm

frm4

cr_fs1_fs3_edges

frm4

cp_fpr_hazard

cp_gpr_hazard

Instruction

fmsub.s

fmul.s

fmv.w.x

fmv.x.w

fnmadd.s

fnmsub.s

fsgnj.s

fsgnjn.s

fsgnjx.s

Type

FR4

X2F

F2X

FR4

RV32

RV64

cp_asm_count

cp_rs1

cp_rd

cp_rs1_edges

cp_fs1

cp_fs2

cp_fs3

cp_fd

cp_fs1_edges

cp_fs2_edges

cp_fs3_edges

cmp_fd_fs1

cmp_fd_fs2

cmp_fd_fs3

cp_frm

cp_csr_fflags

voun

cp_csr_frm

cr_fs1_fs2_edges

frm4

frm

frm4

cr_fs1_fs3_edges

frm4

cp_fpr_hazard

cp_gpr_hazard

Instruction

fsqrt.s

fsub.s

fsw

Type

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_imm_edges

cp_fs1

cp_fs2

cp_fd

cp_fs1_edges

cp_fs2_edges

cmp_fd_fs1

cmp_fd_fs2

cp_frm

cp_csr_fflags

von

cp_csr_frm

cr_fs1_fs2_edges

frm

cp_fpr_hazard

cp_gpr_hazard

5.7.2. D Double-Precision FP

Table 39. D Instruction Coverpoints
Instruction	fadd.d	fclass.d	fcvt.d.l	fcvt.d.lu	fcvt.d.s	fcvt.d.w	fcvt.d.wu	fcvt.l.d	fcvt.lu.d
Type	FR	FIX	X2F	X2F	FI	X2F	X2F	F2X	F2X
RV32	x	x			x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1			x	x		x	x
cp_rd		x						x	x
cp_rs1_edges			x	x		x	x
cp_fs1	x	x			x			x	x
cp_fs2	x
cp_fd	x		x	x	x	x	x
cp_fs1_edges	D	D			x			frm_D	frm_D
cp_fs2_edges	D
cmp_fd_fs1	x				x
cmp_fd_fs2	x
cp_frm	3		2	2				2	2
cp_csr_fflags	von		n	n	v			vn	vn
cp_csr_frm	x		x	x				x	x
cr_fs1_fs2_edges	frm_D
cp_fclass		x
cp_fs1_badNB					D_S
cp_fpr_hazard	rw	r	w	w	rw	w	w	r	r
cp_gpr_hazard		w	r	r		r	r	w	w

Instruction

fcvt.s.d

fcvt.w.d

fcvt.wu.d

fdiv.d

feq.d

fld

fle.d

flt.d

fmadd.d

Type

F2X

FR4

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rd

cp_imm_edges

cp_fs1

cp_fs2

cp_fs3

cp_fd

cp_fs1_edges

frm_D

cp_fs2_edges

cp_fs3_edges

cmp_fd_fs1

cmp_fd_fs2

cmp_fd_fs3

cp_frm

cp_csr_fflags

voun

vdoun

voun

cp_csr_frm

cr_fs1_fs2_edges

frm_D

frm4_D

cr_fs1_fs3_edges

frm4_D

cp_NaNBox

D_S

cp_fpr_hazard

cp_gpr_hazard

Instruction

fmax.d

fmin.d

fmsub.d

fmul.d

fmv.d.x

fmv.x.d

fnmadd.d

fnmsub.d

fsd

Type

FR4

X2F

F2X

FR4

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rd

cp_rs1_edges

cp_imm_edges

cp_fs1

cp_fs2

cp_fs3

cp_fd

cp_fs1_edges

cp_fs2_edges

cp_fs3_edges

cmp_fd_fs1

cmp_fd_fs2

cmp_fd_fs3

cp_frm

cp_csr_fflags

voun

cp_csr_frm

cr_fs1_fs2_edges

frm4_D

frm_D

frm4_D

cr_fs1_fs3_edges

frm4_D

cp_fpr_hazard

cp_gpr_hazard

Instruction

fsgnj.d

fsgnjn.d

fsgnjx.d

fsqrt.d

fsub.d

Type

RV32

RV64

cp_asm_count

cp_fs1

cp_fs2

cp_fd

cp_fs1_edges

cp_fs2_edges

cmp_fd_fs1

cmp_fd_fs2

cp_frm

cp_csr_fflags

von

cp_csr_frm

cr_fs1_fs2_edges

frm_D

cp_fpr_hazard

Instruction

fadd.s

fclass.s

fcvt.l.s

fcvt.lu.s

fcvt.s.l

fcvt.s.lu

fcvt.s.w

fcvt.s.wu

fcvt.w.s

Type

FIX

F2X

X2F

F2X

RV32

RV64

cp_NaNBox

D_S

cp_fs1_badNB

D_S

cp_fs2_badNB

D_S

Instruction

fcvt.wu.s

fdiv.s

feq.s

fle.s

flt.s

flw

fmadd.s

fmax.s

fmin.s

Type

F2X

FR4

RV32

RV64

cp_NaNBox

D_S

cp_fs1_badNB

D_S

cp_fs2_badNB

D_S

cp_fs3_badNB

D_S

Instruction

fmsub.s

fmul.s

fmv.w.x

fmv.x.w

fnmadd.s

fnmsub.s

fsgnj.s

fsgnjn.s

fsgnjx.s

Type

FR4

X2F

F2X

FR4

RV32

RV64

cp_NaNBox

D_S

cp_fs1_badNB

D_S

cp_fs2_badNB

D_S

cp_fs3_badNB

D_S

Instruction

fsqrt.s

fsub.s

fsw

Type

RV32

RV64

cp_NaNBox

D_S

cp_fs1_badNB

D_S

cp_fs2_badNB

D_S

5.7.3. Zfh Half-Precision FP

Table 40. Zfh Instruction Coverpoints
Instruction	fadd.h	fclass.h	fcvt.h.l	fcvt.h.lu	fcvt.h.s	fcvt.h.w	fcvt.h.wu	fcvt.l.h	fcvt.lu.h
Type	FR	FIX	X2F	X2F	FI	X2F	X2F	F2X	F2X
RV32	x	x			x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1			x	x		x	x
cp_rd		x						x	x
cp_rs1_edges			x	x		x	x
cp_fs1	x	x			x			x	x
cp_fs2	x
cp_fd	x		x	x	x	x	x
cp_fs1_edges	H	H			frm			frm_H	frm_H
cp_fs2_edges	H
cmp_fd_fs1	x				x
cmp_fd_fs2	x
cp_frm	3		2	2	2	2	2	2	2
cp_csr_fflags	von		on	on	voun	on	on	vn	vn
cp_csr_frm	x		x	x	x	x	x	x	x
cr_fs1_fs2_edges	frm_H
cp_fclass		x
cp_NaNBox	S_H		S_H	S_H	S_H	S_H	S_H
cp_fs1_badNB	S_H	S_H						S_H	S_H
cp_fs2_badNB	S_H
cp_fpr_hazard	rw	r	w	w	rw	w	w	r	r
cp_gpr_hazard		w	r	r		r	r	w	w

Instruction

fcvt.s.h

fcvt.w.h

fcvt.wu.h

fdiv.h

feq.h

fle.h

flh

flt.h

fmadd.h

Type

F2X

FR4

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_rd

cp_imm_edges

cp_fs1

cp_fs2

cp_fs3

cp_fd

cp_fs1_edges

frm_H

cp_fs2_edges

cp_fs3_edges

cmp_fd_fs1

cmp_fd_fs2

cmp_fd_fs3

cp_frm

cp_csr_fflags

vdoun

voun

cp_csr_frm

cr_fs1_fs2_edges

frm_H

frm4_H

cr_fs1_fs3_edges

frm4_H

cp_NaNBox

S_H

cp_fs1_badNB

S_H

cp_fs2_badNB

S_H

cp_fs3_badNB

S_H

cp_fpr_hazard

cp_gpr_hazard

Instruction

fmax.h

fmin.h

fmsub.h

fmul.h

fmv.h.x

fmv.x.h

fnmadd.h

fnmsub.h

fsgnj.h

Type

FR4

X2F

F2X

FR4

RV32

RV64

cp_asm_count

cp_rs1

cp_rd

cp_rs1_edges

cp_fs1

cp_fs2

cp_fs3

cp_fd

cp_fs1_edges

cp_fs2_edges

cp_fs3_edges

cmp_fd_fs1

cmp_fd_fs2

cmp_fd_fs3

cp_frm

cp_csr_fflags

voun

cp_csr_frm

cr_fs1_fs2_edges

frm4_H

frm_H

frm4_H

cr_fs1_fs3_edges

frm4_H

cp_NaNBox

S_H

cp_fs1_badNB

S_H

cp_fs2_badNB

S_H

cp_fs3_badNB

S_H

cp_fpr_hazard

cp_gpr_hazard

Instruction

fsgnjn.h

fsgnjx.h

fsh

fsqrt.h

fsub.h

Type

RV32

RV64

cp_asm_count

cp_rs1

nx0

cp_imm_edges

cp_fs1

cp_fs2

cp_fd

cp_fs1_edges

cp_fs2_edges

cmp_fd_fs1

cmp_fd_fs2

cp_frm

cp_csr_fflags

von

cp_csr_frm

cr_fs1_fs2_edges

frm_H

cp_NaNBox

S_H

cp_fs1_badNB

S_H

cp_fs2_badNB

S_H

cp_fpr_hazard

cp_gpr_hazard

5.7.3.1. ZfhD

5.7.3.2. Zfhmin

Table 41. Zfhmin Instruction Coverpoints
Instruction	fcvt.h.s	fcvt.s.h	flh	fmv.h.x	fmv.x.h	fsh
Type	FI	FI	FL	X2F	F2X	FS
RV32	x	x	x	x	x	x
RV64	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x
cp_rs1			nx0	x		nx0
cp_rd					x
cp_rs1_edges				x
cp_imm_edges			x			x
cp_fs1	x	x			x
cp_fs2						x
cp_fd	x	x	x	x
cp_fs1_edges	x	H			H
cp_fs2_edges						H
cmp_fd_fs1	x	x
cp_frm	2
cp_csr_fflags	vn	v
cp_csr_frm	x
cp_NaNBox	S_H		S_H	S_H
cp_fs1_badNB		S_H			S_H
cp_fs2_badNB						S_H
cp_fpr_hazard	rw	rw	w	w	r	r
cp_gpr_hazard			r	r	w	r

5.7.3.3. ZfhminD

Table 42. ZfhminD Instruction Coverpoints
Instruction	fcvt.h.s	fcvt.s.h	flh	fmv.h.x	fmv.x.h	fsh
Type	FI	FI	FL	X2F	F2X	FS
RV32	x	x	x	x	x	x
RV64	x	x	x	x	x	x
cp_NaNBox	D_H		D_H	D_H
cp_fs1_badNB		D_H			D_H
cp_fs2_badNB						D_H

5.7.4. Zfa Additional FP

Tests for Zfa for single-precision floating-point are called ZfaF.

Table 43. ZfaF Instruction Coverpoints
Instruction	fleq.s	fli.s	fltq.s	fmaxm.s	fminm.s	fround.s	froundnx.s
Type	FC	FLI	FC	FR	FR	FI	FI
RV32	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x
cp_rs1		fli
cp_rd	x		x
cp_fs1	x		x	x	x	x	x
cp_fs2	x		x	x	x
cp_fd		x		x	x	x	x
cp_fs1_edges	x		x	x	x	x	x
cp_fs2_edges	x		x	x	x
cmp_fd_fs1				x	x	x	x
cmp_fd_fs2				x	x
cp_frm						2	2
cp_csr_fflags	v		v	v	v	v	vn
cp_csr_frm						x	x
cr_fs1_fs2_edges	x		x	x	x
cp_fpr_hazard	r	w	r	rw	rw	rw	rw
cp_gpr_hazard	w		w

5.7.4.1. ZfaD

Table 44. ZfaD Instruction Coverpoints
Instruction	fcvtmod.w.d	fleq.d	fli.d	fltq.d	fmaxm.d	fminm.d	fmvh.x.d	fmvp.d.x	fround.d
Type	F2X	FC	FLI	FC	FR	FR	F2X	PX2F	FI
RV32	x	x	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x			x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1			fli					x
cp_rs2								x
cp_rd	x	x		x			x
cp_rs1_edges								x
cp_rs2_edges								x
cp_fs1	x	x		x	x	x	x		x
cp_fs2		x		x	x	x
cp_fd			x		x	x		x	x
cp_fs1_edges	D	D		D	D	D	D		D
cp_fs2_edges		D		D	D	D
cmp_fd_fs1					x	x			x
cmp_fd_fs2					x	x
cp_frm									2
cp_csr_fflags	vn	v		v	v	v			v
cp_csr_frm									x
cr_fs1_fs2_edges		D		D	D	D
cp_fpr_hazard	r	r	w	r	rw	rw	r	w	rw
cp_gpr_hazard	w	w		w			w	r

Instruction

froundnx.d

Type

RV32

RV64

cp_asm_count

cp_fs1

cp_fd

cp_fs1_edges

cmp_fd_fs1

cp_frm

cp_csr_fflags

cp_csr_frm

cp_fpr_hazard

Instruction

fleq.s

fli.s

fltq.s

fmaxm.s

fminm.s

fround.s

froundnx.s

Type

FLI

RV32

RV64

cp_NaNBox

D_S

cp_fs1_badNB

D_S

cp_fs2_badNB

D_S

5.7.4.2. ZfaZfh

Table 45. ZfaZfh Instruction Coverpoints
Instruction	fleq.h	fli.h	fltq.h	fmaxm.h	fminm.h	fround.h	froundnx.h
Type	FC	FLI	FC	FR	FR	FI	FI
RV32	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x
cp_rs1		fli
cp_rd	x		x
cp_fs1	x		x	x	x	x	x
cp_fs2	x		x	x	x
cp_fd		x		x	x	x	x
cp_fs1_edges	H		H	H	H	H	H
cp_fs2_edges	H		H	H	H
cmp_fd_fs1				x	x	x	x
cmp_fd_fs2				x	x
cp_frm						2	2
cp_csr_fflags	v		v	v	v	v	vn
cp_csr_frm						x	x
cr_fs1_fs2_edges	H		H	H	H
cp_NaNBox		S_H		S_H	S_H	S_H	S_H
cp_fs1_badNB	S_H		S_H	S_H	S_H	S_H	S_H
cp_fs2_badNB	S_H		S_H	S_H	S_H
cp_fpr_hazard	r	w	r	rw	rw	rw	rw
cp_gpr_hazard	w		w

5.7.4.3. ZfaZfhD

When Zfa is supported with both Zfh and D, there are additional NAN-Boxing tests for 16-bit values in 64-bit registers.

Table 46. ZfaZfhD Instruction Coverpoints
Instruction	fleq.h	fli.h	fltq.h	fmaxm.h	fminm.h	fround.h	froundnx.h
Type	FC	FLI	FC	FR	FR	FI	FI
RV32	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x
cp_NaNBox		D_H		D_H	D_H	D_H	D_H
cp_fs1_badNB	D_H		D_H	D_H	D_H	S_H	D_H
cp_fs2_badNB	D_H		D_H	D_H	D_H

5.7.4.4. Zfbfmin Scalar BF16 Converts

5.8. Zb* Bit Manipulation Extensions

***B=Zba+Zbb+Zbs

5.8.1. Zba Bit-Manipulation for Addressing

Table 48. Zba Instruction Coverpoints
Instruction	add.uw	sh1add	sh1add.uw	sh2add	sh2add.uw	sh3add	sh3add.uw	slli.uw
Type	R	R	R	R	R	R	R	IS
RV32		x		x		x
RV64	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x	x	x
cp_rs2	x	x	x	x	x	x	x
cp_rd	x	x	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x	x	x
cp_rs2_edges	x	x	x	x	x	x	x
cr_rs1_rs2_edges	x	x	x	x	x	x	x
cmp_rs1_rs2	x	x	x	x	x	x	x
cmp_rd_rs1	x	x	x	x	x	x	x	x
cmp_rd_rs2	x	x	x	x	x	x	x
cmp_rd_rs1_rs2	x	x	x	x	x	x	x
cp_uimm								x
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	rw	rw

5.8.2. Zbb Basic Bit-Manipulation

Table 49. Zbb Instruction Coverpoints
Instruction	andn	clz	clzw	cpop	cpopw	ctz	ctzw	max	maxu
Type	R	I1	I1	I1	I1	I1	I1	R	R
RV32	x	x		x		x		x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x	x	x	x
cp_rs2	x							x	x
cp_rd	x	x	x	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x	x	x	x
cp_rs2_edges	x							x	x
cr_rs1_rs2_edges	x							x	x
cmp_rs1_rs2	x							x	x
cmp_rd_rs1	x	x	x	x	x	x	x	x	x
cmp_rd_rs2	x							x	x
cmp_rd_rs1_rs2	x							x	x
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	rw	rw	rw

Instruction

min

minu

orc.b

orn

rev8

rol

rolw

ror

rori

Type

RV32

RV64

cp_asm_count

cp_rs1

cp_rs2

cp_rd

cp_rs1_edges

orcb

cp_rs2_edges

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_uimm

cp_gpr_hazard

Instruction

roriw

rorw

sext.b

sext.h

xnor

zext.h

Type

RV32

RV64

cp_asm_count

cp_rs1

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_uimm

cp_gpr_hazard

5.8.3. Zbc Carry-less Multiplication

Table 50. Zbc Instruction Coverpoints
Instruction	clmul	clmulh	clmulr
Type	R	R	R
RV32	x	x	x
RV64	x	x	x
cp_asm_count	x	x	x
cp_rs1	x	x	x
cp_rs2	x	x	x
cp_rd	x	x	x
cp_rs1_edges	x	x	x
cp_rs2_edges	x	x	x
cr_rs1_rs2_edges	x	x	x
cmp_rs1_rs2	x	x	x
cmp_rd_rs1	x	x	x
cmp_rd_rs2	x	x	x
cmp_rd_rs1_rs2	x	x	x
cp_gpr_hazard	rw	rw	rw

5.8.4. Zbs Single-Bit Manipulation

Table 51. Zbs Instruction Coverpoints
Instruction	bclr	bclri	bext	bexti	binv	binvi	bset	bseti
Type	R	IS	R	IS	R	IS	R	IS
RV32	x	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x	x	x
cp_rs2	x		x		x		x
cp_rd	x	x	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x	x	x
cp_rs2_edges	x		x		x		x
cr_rs1_rs2_edges	x		x		x		x
cmp_rs1_rs2	x		x		x		x
cmp_rd_rs1	x	x	x	x	x	x	x	x
cmp_rd_rs2	x		x		x		x
cmp_rd_rs1_rs2	x		x		x		x
cp_uimm		x		x		x		x
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	rw	rw

5.8.5. Zbkb Bit-Manipulation for Cryptography

Table 52. Zbkb Instruction Coverpoints
Instruction	andn	brev8	orn	pack	packh	rev8	rol	ror	rori
Type	R	I1	R	R	R	I1	R	R	IS
RV32	x	x	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x	x	x	x
cp_rs2	x		x	nx0	x		x	x
cp_rd	x	x	x	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x	x	x	x
cp_rs2_edges	x		x	x	x		x	x
cr_rs1_rs2_edges	x		x	x	x		x	x
cmp_rs1_rs2	x		x	nx0	x		x	x
cmp_rd_rs1	x	x	x		x	x	x	x	x
cmp_rd_rs2	x		x	nx0	x		x	x
cmp_rd_rs1_rs2	x		x	nx0	x		x	x
cp_uimm									x
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	rw	rw	rw

Instruction

unzip

xnor

zip

Type

RV32

RV64

cp_asm_count

cp_rs1

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_gpr_hazard

5.8.6. Zbkc Carry-less Multiplication for Cryptography

Table 53. Zbkc Instruction Coverpoints
Instruction	clmul	clmulh
Type	R	R
RV32	x	x
RV64	x	x
cp_asm_count	x	x
cp_rs1	x	x
cp_rs2	x	x
cp_rd	x	x
cp_rs1_edges	x	x
cp_rs2_edges	x	x
cr_rs1_rs2_edges	x	x
cmp_rs1_rs2	x	x
cmp_rd_rs1	x	x
cmp_rd_rs2	x	x
cmp_rd_rs1_rs2	x	x
cp_gpr_hazard	rw	rw

5.8.7. Zbkx Permutation

Table 54. Zbkx Instruction Coverpoints
Instruction	xperm4	xperm8
Type	R	R
RV32	x	x
RV64	x	x
cp_asm_count	x	x
cp_rs1	x	x
cp_rs2	x	x
cp_rd	x	x
cp_rs1_edges	x	x
cp_rs2_edges	x	x
cr_rs1_rs2_edges	x	x
cmp_rs1_rs2	x	x
cmp_rd_rs1	x	x
cmp_rd_rs2	x	x
cmp_rd_rs1_rs2	x	x
cp_gpr_hazard	rw	rw

5.9. Zk* Cryptographic Extensions

5.9.1. Zkne NIST AES Encryption

Table 55. Zkne Instruction Coverpoints
Instruction	aes32esi	aes32esmi	aes64es	aes64esm	aes64ks1i	aes64ks2
Type	RB	RB	R	R	IR	R
RV32	x	x
RV64			x	x	x	x
cp_asm_count	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x
cp_rs2	x	x	x	x		x
cp_rd	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x
cp_rs2_edges	x	x	x	x		x
cr_rs1_rs2_edges	x	x	x	x		x
cmp_rs1_rs2	x	x	x	x		x
cmp_rd_rs1	x	x	x	x	x	x
cmp_rd_rs2	x	x	x	x		x
cmp_rd_rs1_rs2	x	x	x	x		x
cp_bs	x	x
cp_rnum					x
cp_gpr_hazard	rw	rw	rw	rw	rw	rw
cp_sbox	x	x	x	x

5.9.2. Zknd NIST AES Decryption

Table 56. Zknd Instruction Coverpoints
Instruction	aes32dsi	aes32dsmi	aes64ds	aes64dsm	aes64im
Type	RB	RB	R	R	I1
RV32	x	x
RV64			x	x	x
cp_asm_count	x	x	x	x	x
cp_rs1	x	x	x	x	x
cp_rs2	x	x	x	x
cp_rd	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x
cp_rs2_edges	x	x	x	x
cr_rs1_rs2_edges	x	x	x	x
cmp_rs1_rs2	x	x	x	x
cmp_rd_rs1	x	x	x	x	x
cmp_rd_rs2	x	x	x	x
cmp_rd_rs1_rs2	x	x	x	x
cp_bs	x	x
cp_gpr_hazard	rw	rw	rw	rw	rw
cp_sbox	x	x	x	x

5.9.3. Zknh NIST SHA2 Hashing

Table 57. Zknh Instruction Coverpoints
Instruction	sha256sig0	sha256sig1	sha256sum0	sha256sum1	sha512sig0	sha512sig0h	sha512sig0l	sha512sig1	sha512sig1h
Type	I1	I1	I1	I1	I1	R	R	R	R
RV32	x	x	x	x		x	x		x
RV64	x	x	x	x	x			x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_rs1	x	x	x	x	x	x	x	x	x
cp_rs2						x	x		x
cp_rd	x	x	x	x	x	x	x	x	x
cp_rs1_edges	x	x	x	x	x	x	x	x	x
cp_rs2_edges						x	x		x
cr_rs1_rs2_edges						x	x		x
cmp_rs1_rs2						x	x		x
cmp_rd_rs1	x	x	x	x	x	x	x	x	x
cmp_rd_rs2						x	x		x
cmp_rd_rs1_rs2						x	x		x
cp_gpr_hazard	rw	rw	rw	rw	rw	rw	rw	rw	rw

Instruction

sha512sig1l

sha512sum0

sha512sum0r

sha512sum1

sha512sum1r

Type

RV32

RV64

cp_asm_count

cp_rs1

cp_rs2

cp_rd

cp_rs1_edges

cp_rs2_edges

cr_rs1_rs2_edges

cmp_rs1_rs2

cmp_rd_rs1

cmp_rd_rs2

cmp_rd_rs1_rs2

cp_gpr_hazard

5.10. Zi* Additional Unpriv Extensions

5.10.1. Zicsr Control/Status Register Instructions

Table 58. Zicsr Instruction Coverpoints
Instruction	csrrc	csrrci	csrrs	csrrsi	csrrw	csrrwi
Type	CSR	CSRI	CSR	CSRI	CSR	CSRI
RV32	x	x	x	x	x	x
RV64	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x
cp_rs1	x		x		x
cp_rd	x	x	x	x	x	x
cp_rs1_edges	x		x		x
cmp_rd_rs1	x		x		x
cp_uimm		5		5		5
cp_gpr_hazard	rw	w	rw	w	rw	w

5.10.2. Zifencei Instruction-Fetch Fence

Table 59. Zifencei Instruction Coverpoints
Instruction	fence.i
Type	I
RV32	x
RV64	x
cp_asm_count	x
cp_custom	fencei

5.10.3. Zicond Conditional Instructions

Table 60. Zicond Instruction Coverpoints
Instruction	czero.eqz	czero.nez
Type	R	R
RV32	x	x
RV64	x	x
cp_asm_count	x	x
cp_rs1	x	x
cp_rs2	x	x
cp_rd	x	x
cp_rs1_edges	x	x
cp_rs2_edges	x	x
cr_rs1_rs2_edges	x	x
cmp_rs1_rs2	x	x
cmp_rd_rs1	x	x
cmp_rd_rs2	x	x
cmp_rd_rs1_rs2	x	x
cp_gpr_hazard	rw	rw

5.10.4. Zihintpause Pause Hint

Table 61. Zihintpause Instruction Coverpoints
Instruction	pause
Type	I
RV32	x
RV64	x
cp_asm_count	x
cp_custom	pause

5.10.5. Zihintntl Non-temporal Locality Hint

5.10.6. ZihintntlZca Compressed Non-temporal Locality Hint

5.10.7. Zicbom Cache Block Flush/Invalidate

5.10.8. Zicboz Cache Block Zero

5.10.9. Zicbop Cache Block Prefetch

5.10.10. Za64rs Max 64B Reservation Set

5.10.11. Zic64bZicboz 64B Cache Block Zero

5.11. V Vector Extension

The vector coverpoints are intended to be flexible to support the full V extension, the Zve* embedded vector extensions, and arbitrary mixes of supported vector length (VLEN), element lengths (SEW_MIN, ELEN), and floating-point precisions.

The vector extension is huge. The testplan is partitioned into three unprivileged portions discussed here, and three privileged portions (ZicsrV, ExceptionsV, SsstrictV) discussed in XREF.

The full V extension supports all selected element widths SEW={8, 16, 32, 64}. The vector coverage files and tests are organized by SEW. Thus, a DUT could handle any contiguous subset of SEW from SEW_MIN to ELEN. For example, a DUT with SEW_MIN=16 and ELEN=32 would support SEW={16, 32}.

The tests detect VLMAX and set the vector length accordingly, up to some configurable maximum VLEN (default 4096 bits, although the vector extension theoretically supports up to 65536). Therefore, there is no need for different test suites for different VLENs.

5.11.1. Vector File Organization

Listing 1 summarizes the structure of the coverpoint and test files for the vector extension. The unprivileged vector tests are organized by integer (Vx), load/store (Vls), and floating-point (Vf) types of instructions. Each applies to SEW=8, 16, 32, and/or 64. The ExceptionsV, ZicsrV, and SsstrictV privileged tests are described in section XREF.

The vector tests are organized by XLEN=32 and XLEN=64 because the scalar registers behavior differs by XLEN. For example, vadd.vx with SEW=64 sign-extends XLEN=32 scalar registers but does not modify XLEN=64 scalar registers. For a given XLEN, the vector tests are organized by type (Vx/Vls/Vf) and SEW (8/16/32/64). Each directory contains a .S file for every vector instruction of that type ^[5]. Vector load/store instructions run with any SEW but also specify EEW as part of the instruction name. For example, vle8.v and vle16.v can both be executed in either SEW=8 or SEW=16, and the EMUL behavior is different between these modes. Therefore, all the load/store variants are included in all of Vls{8/16/32/64}.

Vx and Vf are separated because certain extensions such as Zve64x do not support floating-point. Vls could be lumped with Vx, but the coverpoints are so different that it is easier to define the tests separately, and facilitates just running integer vs. load/store tests during development.

Listing 1. Vector Organization

fcov
    unpriv
        Vx8_coverage.svh
        Vx16_coverage.svh
        Vx32_coverage.svh
        Vx64_coverage.svh
        Vls8_coverage.svh
        Vls16_coverage.svh
        Vls32_coverage.svh
        Vls64_coverage.svh
        Vf16_coverage.svh
        Vf32_coverage.svh
        Vf64_coverage.svh
      priv
        ExceptionsV_coverage.svh
        ZicsrV_coverage.svh
        SsstrictV_coverage.svh
tests
    rv32
        Vx8
            vadd.vv.S
            vadd.vx.S
            vadd.vi.S
            vsub.vv.S
            ...
        Vx16
            vadd.vv.S
            ...
        Vx32
            vadd.vv.S
            ...
        Vx64
            vadd.vv.S
            ...
        Vls8
            vle8.v.S
            vle16.v.S
            vle32.v.S
            vle64.v.S
            vlseg2e8.v.S
            ...
        Vls16
            vle8.v.S
            ...
        Vls32
            vle8.v.S
            ...
        Vls64
            vle8.v.S
            ...
        Vf16
            vfadd.vv.S
            vfadd.vf.S
            vfwadd.vv.S
            vfsub.vv.S
            ...
        Vf32
            vfadd.vv.S
            ...
        Vf64
            vfadd.vv.S
            ...
    rv64
        Vx8
        Vx16
        Vx32
        Vx64
        Vls8
        Vls16
        Vls32
        Vls64
        Vf16
        Vf32
        Vf64
    priv
        ExceptionsV.S
        ZicsrV.S
        SsstrictV.S

When an instruction’s EEW is not a supported SEW, the coverage files and tests exclude the instruction from testing. For example, vwadd.vv is not supported when SEW=32 and ELEN = 32 because it cannot widen to 64 bits.

The tests also account for unsupported register group overlap. For example, a widening add vwadd.wv v0, v2, v2 is unspported because the source registers cannot be read with different EEWs. On the other hand vwadd.vv v0, v1, v8 with LMUL=1 is supported even though the destination vd=v0 widens to write [v0-v1], which overlaps with vs2=v1. The tests exercise all supported overlaps, but do not attempt any unsupported overlaps because the behavior is reserved and unpredictable.

5.11.2. Vector Configuration Parameters

The coverpoints and tests are parameterized by the minimum supported element width SEW_MIN and the maximum supported element width ELEN. The coverpoints and tests exclude unsupported edge cases, such as widening to more than ELEN or using LMUL=1/8 with ELEN=32 but SEW_MIN=8.

5.11.3. Vector Coverpoints

Running long vectors is computationally expensive, so only a subset of vectors tests run on mult-element vectors. Coverpoints for source and destination registers, edge values, etc. run on a vector length of vl = 1.

Table 69 defines the coverpoints used in vector instructions. Unless otherwise specified, each coverpoint uses vector length vl=1 and length multiplier LMUL=1, no mask (vm=1), and vstart=0. Hence, they act on exactly one vector element. For such coverpoints, instructions that require a mask use v0=0.

Table 69. Vector Coverpoint Definitions
Coverpoint	# Bins	Definition
Coverpoints acting on single element vl=1
cp_vd	32	All vector destination registers vd=0-31
cp_vs2	32	All vector source registers vs2=0-31
cp_vs1	32	All vector source registers vs1=0-31
cp_vs3	32	All vector source registers vs3=0-31
cp_rs1	32	All scalar registers rs1=0-31
cp_rs2	32	All scalar registers rs2=0-31
cp_imm_5bit	32	Signed immediate values -16 to +15
cmp_rs1_rs2	32	rs1 and rs2 are same register ID
cmp_vd_vs2	32	vd and vs2 are same register ID
cmp_vd_vs1	32	vd and vs1 are same register ID
cmp_vs2_vs1	32	vs2 and vs1 are same register ID
cmp_vs3_vs2	32	vs3 and vs2 are the same register ID
cmp_vd_vs1_vs2	32	vd and vs1 and vs2 are same register ID
cp_rs1_edges	9	0, 1, 2, -1, -2, most negative, most negative+1, most positive, most positive-1
cp_rs2_edges	5	0, 1, 2, -1, -2 (for strided vector load/store)
cp_fs1_edges	20	0, -1, -smallest subnorm, -inf, 1, 1+ulp, 0.5, 1.5, 2, 4, pi, 2^emax, largest normal, smallest normal, largest subnormal, subnormal with leading 1 in fraction, infinity, canonical quite NaN, noncanonical quiet NaN, signaling NaN with payload of 1
cp_vs2_edges	9 or 20	see cp_rs1_edges or cp_fs1_edges
cp_vs1_edges	9 or 20	see cp_rs1_edges
cr_vs2_vs1_edges	9^2 or 20^2	Cross-product of edges of vs2 and vs1
cr_vs2_rs1_edges	9*9	Cross-product of edges of vs2 and rs1
cr_vs2_fs1_edges	20*20	Cross-product of edges of vs2 and fs1
cr_vs2_imm_edges	9*9	Cross-product of edges of vs2 and imm={0, 1, 2, 14, 15, -1, -2, -15,-16}
cr_vxrm_vs2_vs1_edges	994	Cross-product of edges of vs2 and vs1 with vector rounding mode={rod, rdn, rne, rnu}
cr_vxrm_vs2_rs1_edges	994	See cr_vxrm_vs2_vs1_edges
cr_vxrm_vs2_imm_edges	994	See cr_vxrm_vs2_vs1_edges
cp_csr_frm	5*10	Floating-point rounding mode={rdn, rmm, rne, rtz, rup} with 10 random inputs per mode
cp_csr_fflags	5*2	Floating-point sets and clears all applicable flags
Coverpoints acting on multiple elements vl ≠ 1
cp_masking_edges	5	Mask edge cases v0=all 1s, all 0s, random, first VLMAX-1 ones, first VLMAX/2+1 ones; vl=VLMAX, vm=1 to mask, vma = random, vta = 0
cr_vl_lmul	7*3	Cross legal combinations of LMUL={1/2/4/8/f2/f4/f8} and vl={1, random, VLMAX}, while randomizing v0 mask value, vm, vta, vma.
cr_vtype_agnostic	4	Cross vta={0/1} and vma={0/1}. Random legal LMUL, random legal vl, vm=1, v0=random mask
cp_vxsat	2	vxsat={0, 1}. Hit by cr_vs2_vs1_edges so no tests needed.
cp_vl_0	1	vl=0. LMUL=1, no mask, vma=0, vta=1

As with other unprivileged testplans, an x in the spreadsheet indicates to use the coverpoint. Other values in the spreadsheet indicate a variant of the coverpoint:

nv0: Do not include v0 in the coverpoint. For example, cp_vd_nv0 means that the destination register vd does not include v0.
emul2: Only exercise even-numbered registers. For example cp_vs2_emul2 uses vs2={v0, v2, v4, …v30}. For edge values, emul2 means the edge value is twice the width of SEW.
emul4/8: Similar to emul2
emulf2, emulf4, emulf8: edge values are 1/2, 1/4, or 1/8 the width of SEW. Used in extension instructions such as vsext.vf2.
u: Treat immediate as unsigned 0 to 31 rather than signed -16 to +15. For edge values, {0, 1, 2, 15, 16, 30, 31}.
eew1/mm: Mask instructions with 1-bit elements such as vmand.mm use at least vl=8 to operate on multi-bit masks.
wv: vs2 is double-width and uses emul2 for its edge values. vs1 is normal width.
wred: vs1 is double-width and uses emul2 for its edge values. vs2 is normal width.
wx: vs2 is double-width and uses emul2 for its edge values. rs1 is normal width.
wi/wiu: vs2 is double-width and uses emul2 for its edge values. immediate is 5 bit signed or unsigned.
lmul4max/emul4max: maximum LMUL/EMUL is 4 instead of 8. vwadd.vv uses lmul4max because it cannot accept LMUL=8 widened to 16. vlseg2e8.v uses emul4max because the number of segments * EMUL cannot exceed 8.
lmul2max/lmul1max/emul2max/emul1max: see lmul4max
lte30/…/lte24: Register number is less than or equal to 30, …, 24. Used for segmented load/store so segments won’t overflow the register file.
ls_e{8/16/32/64}: load/store edges with EEW=8,…,64. Used to convert strided loads from elements to bytes.
ls: load/store edges instead of integer edges: vs2={0, random < 2*VLMAX}. rs2= {1, 2, -1, -2, 0}
f: floating-point edges instead of integer edges: *
- discuss special cases

The coverpoints for each vector instruction are given in the following sections.

5.11.4. Vx

The Vx testplan is the same for SEW={8, 16, 32, 64}. Each SEW has its own coverage file (e.g. Vx8_coverages.svh) independent of XLEN, as well as tests that depend on XLEN (e.g. rv32/Vx8/vadd.vx.S).

Table 70. Vx Instruction Coverpoints
Instruction	vadd.vv	vadd.vx	vadd.vi	vwadd.vv	vwadd.vx	vwaddu.vv	vwaddu.vx	vwadd.wv	vwadd.wx
Type	VVVM	VVXM	VVIM	VVVM	VVXM	VVVM	VVXM	VVVM	VVXM
RV32	x	x	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x	x	x
EFFEW8	x	x	x	x	x	x	x	x	x
EFFEW16	x	x	x	x	x	x	x	x	x
EFFEW32	x	x	x	x	x	x	x	x	x
EFFEW64	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_vd	x	x	x	emul2	emul2	emul2	emul2	emul2	emul2
cp_vs2	x	x	x	x	x	x	x	emul2	emul2
cp_vs1	x			x		x		x
cp_rs1		x			x		x		x
cp_imm_5bit			x
cmp_vd_vs2	x	x	x					emul2	emul2
cmp_vd_vs1	x
cmp_vs1_vs2	x			x		x
cmp_vd_vs1_vs2	x
cp_vs2_edges	x	x	x	x	x	x	x	emul2	emul2
cp_vs1_edges	x			x		x		x
cr_vs2_vs1_edges	x			x		x		wv
cp_rs1_edges		x			x		x		x
cr_vs2_rs1_edges		x			x		x		wx
cr_vs2_imm_edges			x
cp_masking_edges	x	x	x	x	x	x	x	x	x
cr_vl_lmul	x	x	x	lmul4max	lmul4max	lmul4max	lmul4max	lmul4max	lmul4max
cr_vtype_agnostic	x	x	x	lmul4max	lmul4max	lmul4max	lmul4max	lmul4max	lmul4max
cp_vl_0	x	x	x	x	x	x	x	x	x
cp_custom				wvv_all	wvx_all	wvv	wvx	wwv_all

Instruction

vwaddu.wv

vwaddu.wx

vsub.vv

vsub.vx

vwsub.vv

vwsub.vx

vwsubu.vv

vwsubu.vx

vwsub.wv

Type

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

emul2

cp_vs1

cp_rs1

cmp_vd_vs2

emul2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

emul2

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

wwv

wvv

wvx

wvv

wvx

wwv

Instruction

vwsub.wx

vwsubu.wv

vwsubu.wx

vrsub.vx

vrsub.vi

vzext.vf2

vzext.vf4

vzext.vf8

vsext.vf2

Type

VVXM

VVVM

VVXM

VVIM

VVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

emul2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

emul2

cp_vs2_edges

emul2

emulf2

emulf4

emulf8

emulf2

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

wwv

vext2

vext4

vext8

vext2

Instruction

vsext.vf4

vsext.vf8

vadc.vvm

vadc.vxm

vadc.vim

vsbc.vvm

vsbc.vxm

vmadc.vvm

vmadc.vxm

Type

VVM

VVVM

VVXM

VVIM

VVVM

VVXM

VVVM

VVXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

nv0

cp_vs2

nv0

cp_vs1

nv0

cp_rs1

cp_imm_5bit

cmp_vd_vs2

nv0

cmp_vd_vs1

nv0

cmp_vs1_vs2

nv0

cmp_vd_vs1_vs2

nv0

cp_vs2_edges

emulf4

emulf8

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_custom

vext4

vext8

maskwrite_masked

Instruction

vmadc.vim

vmadc.vv

vmadc.vx

vmadc.vi

vmsbc.vvm

vmsbc.vxm

vmsbc.vv

vmsbc.vx

vand.vv

Type

VVIM

VVV

VVX

VVI

VVVM

VVXM

VVV

VVX

VVVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

nv0

cp_vs1

nv0

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

nv0

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

nomask

cp_vl_0

cp_custom

maskwrite_masked

maskwrite_unmasked

maskwrite_masked

maskwrite_unmasked

Instruction

vand.vx

vand.vi

vor.vv

vor.vx

vor.vi

vxor.vv

vxor.vx

vxor.vi

vsll.vv

Type

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_custom

shift_vv

Instruction

vsll.vx

vsll.vi

vsrl.vv

vsrl.vx

vsrl.vi

vnsrl.wv

vnsrl.wx

vnsrl.wi

vsra.vv

Type

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

emul2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

emul2

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

wiu

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

shift_vx

shift_vv

shift_vx

shift_wv

shift_wx

shift_wi

shift_vv

Instruction

vsra.vx

vsra.vi

vnsra.wv

vnsra.wx

vnsra.wi

vmseq.vv

vmseq.vx

vmseq.vi

vmsne.vv

Type

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

emul2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cp_vs2_edges

emul2

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

wiu

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

shift_vx

shift_wv

shift_wx

shift_wi

maskwrite_masked

Instruction

vmsne.vx

vmsne.vi

vmslt.vv

vmslt.vx

vmsltu.vv

vmsltu.vx

vmsle.vv

vmsle.vx

vmsle.vi

Type

VVXM

VVIM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVIM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_custom

maskwrite_masked

Instruction

vmsleu.vv

vmsleu.vx

vmsleu.vi

vmsgt.vx

vmsgt.vi

vmsgtu.vx

vmsgtu.vi

vmin.vv

vmin.vx

Type

VVVM

VVXM

VVIM

VVXM

VVIM

VVXM

VVIM

VVVM

VVXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_custom

maskwrite_masked

Instruction

vminu.vv

vminu.vx

vmax.vv

vmax.vx

vmaxu.vv

vmaxu.vx

vmul.vv

vmul.vx

vmulh.vv

Type

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_rs1

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

Instruction

vmulh.vx

vmulhu.vv

vmulhu.vx

vmulhsu.vv

vmulhsu.vx

vwmul.vv

vwmul.vx

vwmulu.vv

vwmulu.vx

Type

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

cp_vs1

cp_rs1

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

wvv

wvx

wvv

wvx

Instruction

vwmulsu.vv

vwmulsu.vx

vdiv.vv

vdiv.vx

vdivu.vv

vdivu.vx

vrem.vv

vrem.vx

vremu.vv

Type

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

cp_vs1

cp_rs1

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

wvv

wvx

Instruction

vremu.vx

vmacc.vv

vmacc.vx

vnmsac.vv

vnmsac.vx

vmadd.vv

vmadd.vx

vnmsub.vv

vnmsub.vx

Type

VVXM

VVVMR

VXVM

VVVMR

VXVM

VVVMR

VXVM

VVVMR

VXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_rs1

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

Instruction

vwmacc.vv

vwmacc.vx

vwmaccu.vv

vwmaccu.vx

vwmaccsu.vv

vwmaccsu.vx

vwmaccus.vx

vmerge.vvm

vmerge.vxm

Type

VVVMR

VXVM

VVVMR

VXVM

VVVMR

VXVM

VVVM

VVXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

nv0

cp_vs2

nv0

cp_vs1

nv0

cp_rs1

cmp_vd_vs2

nv0

cmp_vd_vs1

nv0

cmp_vs1_vs2

nv0

cmp_vd_vs1_vs2

nv0

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

wvv

wvx

wvv

wvx

wvv

wvx

Instruction

vmerge.vim

vmv.v.v

vmv.v.x

vmv.v.i

vsadd.vv

vsadd.vx

vsadd.vi

vsaddu.vv

vsaddu.vx

Type

VVIM

VVR

VVVM

VVXM

VVIM

VVVM

VVXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

nv0

cp_vs2

nv0

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

nv0

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

nomask

cp_vl_0

Instruction

vsaddu.vi

vssub.vv

vssub.vx

vssubu.vv

vssubu.vx

vaadd.vv

vaadd.vx

vaaddu.vv

vaaddu.vx

Type

VVIM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cr_vxrm_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vxrm_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

Instruction

vasub.vv

vasub.vx

vasubu.vv

vasubu.vx

vsmul.vv

vsmul.vx

vssrl.vv

vssrl.vx

vssrl.vi

Type

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVVM

VVXM

VVIM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cr_vxrm_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vxrm_vs2_rs1_edges

cr_vs2_imm_edges

cr_vxrm_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_custom

shift_vv

shift_vx

Instruction

vssra.vv

vssra.vx

vssra.vi

vnclip.wv

vnclip.wx

vnclip.wi

vnclipu.wv

vnclipu.wx

vnclipu.wi

Type

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

VVVM

VVXM

VVIM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

emul2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

emul2

cp_vs1_edges

cr_vs2_vs1_edges

cr_vxrm_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vxrm_vs2_rs1_edges

cr_vs2_imm_edges

wiu

cr_vxrm_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

shift_vv

shift_vx

shift_wv

shift_wx

shift_wi

shift_wv

shift_wx

shift_wi

Instruction

vredsum.vs

vwredsum.vs

vwredsumu.vs

vredmax.vs

vredmaxu.vs

vredmin.vs

vredminu.vs

vredand.vs

vredor.vs

Type

VVVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

cp_vs1

emul2

cmp_vd_vs2

cmp_vd_vs1

emul2

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

emul2

cr_vs2_vs1_edges

wred

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_custom

red

wred

red

Instruction

vredxor.vs

vmand.mm

vmnand.mm

vmandn.mm

vmxor.mm

vmor.mm

vmnor.mm

vmorn.mm

vmxnor.mm

Type

VVVM

VVV

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

eew1

cp_vs1_edges

eew1

cr_vs2_vs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

nomask

cp_vl_0

cp_custom

red

maskwrite_unmasked

Instruction

vcpop.m

vfirst.m

vmsbf.m

vmsif.m

vmsof.m

viota.m

vid.v

vmv.x.s

vmv.s.x

Type

XVM

VVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_rd

cp_vs2

cp_rs1

cp_vs2_edges

eew1

cp_rs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

nomask

cp_vl_0

cp_custom

gprwrite

maskwrite_unmasked

vmv_x_s

vmv_s_x

Instruction

vslideup.vx

vslideup.vi

vslidedown.vx

vslidedown.vi

vslide1up.vx

vslide1down.vx

vrgather.vv

vrgather.vx

vrgather.vi

Type

VVXM

VVIM

VVXM

VVIM

VVXM

VVVM

VVXM

VVIM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_rs1

cp_imm_5bit

cmp_vd_vs2

cmp_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_rs1_edges

cr_vs2_rs1_edges

cr_vs2_imm_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_custom

vindexVX

vindexVV

vindexVX

Instruction

vrgatherei16.vv

vcompress.vm

vmv1r.v

vmv2r.v

vmv4r.v

vmv8r.v

Type

VVVM

VVV

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

emul4

emul8

cp_vs2

emul2

emul4

emul8

cp_vs1

cmp_vd_vs2

emul2

emul4

emul8

cmp_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

nomask

cp_vl_0

cp_custom

vindexVV

5.11.5. Vls

Table 71. Vls Instruction Coverpoints
Instruction	vle8.v	vle16.v	vle32.v	vle64.v	vlseg2e8.v	vlseg2e16.v	vlseg2e32.v	vlseg2e64.v	vlseg3e8.v
Type	VXM	VXM	VXM	VXM	VXM	VXM	VXM	VXM	VXM
RV32	x	x	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x	x	x
EFFEW8	x	x	x	x	x	x	x	x	x
EFFEW16	x	x	x	x	x	x	x	x	x
EFFEW32	x	x	x	x	x	x	x	x	x
EFFEW64	x	x	x	x	x	x	x	x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_vd	x	x	x	x	lte30	lte30	lte30	lte30	lte29
cp_rs1	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0	nx0
cp_masking_edges	x	x	x	x	x	x	x	x	x
cr_vl_lmul	e8	e16	e32	e64	e8_emul4max	e16_emul4max	e32_emul4max	e64_emul4max	e8_emul2max
cr_vtype_agnostic	e8	e16	e32	e64	e8_emul4max	e16_emul4max	e32_emul4max	e64_emul4max	e8_emul2max
cp_vl_0	x	x	x	x	x	x	x	x	x

Instruction

vlseg3e16.v

vlseg3e32.v

vlseg3e64.v

vlseg4e8.v

vlseg4e16.v

vlseg4e32.v

vlseg4e64.v

vlseg5e8.v

vlseg5e16.v

Type

VXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte29

lte28

lte27

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

cr_vtype_agnostic

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

cp_vl_0

Instruction

vlseg5e32.v

vlseg5e64.v

vlseg6e8.v

vlseg6e16.v

vlseg6e32.v

vlseg6e64.v

vlseg7e8.v

vlseg7e16.v

vlseg7e32.v

Type

VXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte27

lte26

lte25

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cr_vtype_agnostic

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cp_vl_0

Instruction

vlseg7e64.v

vlseg8e8.v

vlseg8e16.v

vlseg8e32.v

vlseg8e64.v

vle8ff.v

vle16ff.v

vle32ff.v

vle64ff.v

Type

VXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte25

lte24

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e16

e32

e64

cr_vtype_agnostic

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e16

e32

e64

cp_vl_0

Instruction

vlseg2e8ff.v

vlseg2e16ff.v

vlseg2e32ff.v

vlseg2e64ff.v

vlseg3e8ff.v

vlseg3e16ff.v

vlseg3e32ff.v

vlseg3e64ff.v

vlseg4e8ff.v

Type

VXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte30

lte29

lte28

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

cr_vtype_agnostic

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

cp_vl_0

Instruction

vlseg4e16ff.v

vlseg4e32ff.v

vlseg4e64ff.v

vlseg5e8ff.v

vlseg5e16ff.v

vlseg5e32ff.v

vlseg5e64ff.v

vlseg6e8ff.v

vlseg6e16ff.v

Type

VXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte28

lte27

lte26

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cr_vtype_agnostic

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cp_vl_0

Instruction

vlseg6e32ff.v

vlseg6e64ff.v

vlseg7e8ff.v

vlseg7e16ff.v

vlseg7e32ff.v

vlseg7e64ff.v

vlseg8e8ff.v

vlseg8e16ff.v

vlseg8e32ff.v

Type

VXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte26

lte25

lte24

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cr_vtype_agnostic

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cp_vl_0

Instruction

vlseg8e64ff.v

vlse8.v

vlse16.v

vlse32.v

vlse64.v

vlsseg2e8.v

vlsseg2e16.v

vlsseg2e32.v

vlsseg2e64.v

Type

VXM

VXXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte24

lte30

cp_rs1

nx0

cp_rs2

cp_rs2_edges

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

cp_masking_edges

cr_vl_lmul

e64_emul1max

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

cr_vtype_agnostic

e64_emul1max

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

cp_vl_0

Instruction

vlsseg3e8.v

vlsseg3e16.v

vlsseg3e32.v

vlsseg3e64.v

vlsseg4e8.v

vlsseg4e16.v

vlsseg4e32.v

vlsseg4e64.v

vlsseg5e8.v

Type

VXXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte29

lte28

lte27

cp_rs1

nx0

cp_rs2

cp_rs2_edges

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

cp_masking_edges

cr_vl_lmul

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

cr_vtype_agnostic

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

cp_vl_0

Instruction

vlsseg5e16.v

vlsseg5e32.v

vlsseg5e64.v

vlsseg6e8.v

vlsseg6e16.v

vlsseg6e32.v

vlsseg6e64.v

vlsseg7e8.v

vlsseg7e16.v

Type

VXXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte27

lte26

lte25

cp_rs1

nx0

cp_rs2

cp_rs2_edges

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

cp_masking_edges

cr_vl_lmul

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cr_vtype_agnostic

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cp_vl_0

Instruction

vlsseg7e32.v

vlsseg7e64.v

vlsseg8e8.v

vlsseg8e16.v

vlsseg8e32.v

vlsseg8e64.v

vluxei8.v

vluxei16.v

vluxei32.v

Type

VXXM

VXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte25

lte24

cp_vs2

cp_vs2_edges

cmp_vd_vs2

sew_lte_8

sew_lte_16

sew_lte_32

cp_rs1

nx0

cp_rs2

cp_rs2_edges

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

cp_masking_edges

cr_vl_lmul

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e16

e32

cr_vtype_agnostic

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e16

e32

cp_vl_0

Instruction

vluxei64.v

vluxseg2ei8.v

vluxseg2ei16.v

vluxseg2ei32.v

vluxseg2ei64.v

vluxseg3ei8.v

vluxseg3ei16.v

vluxseg3ei32.v

vluxseg3ei64.v

Type

VXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte30

lte29

cp_vs2

cp_vs2_edges

cmp_vd_vs2

sew_lte_64

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

cr_vtype_agnostic

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

cp_vl_0

Instruction

vluxseg4ei8.v

vluxseg4ei16.v

vluxseg4ei32.v

vluxseg4ei64.v

vluxseg5ei8.v

vluxseg5ei16.v

vluxseg5ei32.v

vluxseg5ei64.v

vluxseg6ei8.v

Type

VXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte28

lte27

lte26

cp_vs2

cp_vs2_edges

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cr_vtype_agnostic

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cp_vl_0

Instruction

vluxseg6ei16.v

vluxseg6ei32.v

vluxseg6ei64.v

vluxseg7ei8.v

vluxseg7ei16.v

vluxseg7ei32.v

vluxseg7ei64.v

vluxseg8ei8.v

vluxseg8ei16.v

Type

VXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte26

lte25

lte24

cp_vs2

cp_vs2_edges

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cr_vtype_agnostic

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

cp_vl_0

Instruction

vluxseg8ei32.v

vluxseg8ei64.v

vloxei8.v

vloxei16.v

vloxei32.v

vloxei64.v

vloxseg2ei8.v

vloxseg2ei16.v

vloxseg2ei32.v

Type

VXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte24

lte30

cp_vs2

cp_vs2_edges

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e32_emul1max

e64_emul1max

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

cr_vtype_agnostic

e32_emul1max

e64_emul1max

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

cp_vl_0

Instruction

vloxseg2ei64.v

vloxseg3ei8.v

vloxseg3ei16.v

vloxseg3ei32.v

vloxseg3ei64.v

vloxseg4ei8.v

vloxseg4ei16.v

vloxseg4ei32.v

vloxseg4ei64.v

Type

VXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte30

lte29

lte28

cp_vs2

cp_vs2_edges

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

cr_vtype_agnostic

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

cp_vl_0

Instruction

vloxseg5ei8.v

vloxseg5ei16.v

vloxseg5ei32.v

vloxseg5ei64.v

vloxseg6ei8.v

vloxseg6ei16.v

vloxseg6ei32.v

vloxseg6ei64.v

vloxseg7ei8.v

Type

VXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte27

lte26

lte25

cp_vs2

cp_vs2_edges

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cr_vtype_agnostic

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cp_vl_0

Instruction

vloxseg7ei16.v

vloxseg7ei32.v

vloxseg7ei64.v

vloxseg8ei8.v

vloxseg8ei16.v

vloxseg8ei32.v

vloxseg8ei64.v

vse8.v

vse16.v

Type

VXVM

VSXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

lte25

lte24

cp_vs3

cp_vs2

cp_vs2_edges

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e16

cr_vtype_agnostic

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e16

cp_vl_0

Instruction

vse32.v

vse64.v

vsseg2e8.v

vsseg2e16.v

vsseg2e32.v

vsseg2e64.v

vsseg3e8.v

vsseg3e16.v

vsseg3e32.v

Type

VSXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte30

lte29

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

cr_vtype_agnostic

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

cp_vl_0

Instruction

vsseg3e64.v

vsseg4e8.v

vsseg4e16.v

vsseg4e32.v

vsseg4e64.v

vsseg5e8.v

vsseg5e16.v

vsseg5e32.v

vsseg5e64.v

Type

VSXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte29

lte28

lte27

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

Instruction

vsseg6e8.v

vsseg6e16.v

vsseg6e32.v

vsseg6e64.v

vsseg7e8.v

vsseg7e16.v

vsseg7e32.v

vsseg7e64.v

vsseg8e8.v

Type

VSXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte26

lte25

lte24

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cr_vtype_agnostic

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

cp_vl_0

Instruction

vsseg8e16.v

vsseg8e32.v

vsseg8e64.v

vsse8.v

vsse16.v

vsse32.v

vsse64.v

vssseg2e8.v

vssseg2e16.v

Type

VSXM

VSXXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte24

lte30

cp_rs1

nx0

cp_rs2

cp_rs2_edges

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

cp_masking_edges

cr_vl_lmul

e16_emul1max

e32_emul1max

e64_emul1max

e16

e32

e64

e8_emul4max

e16_emul4max

cr_vtype_agnostic

e16_emul1max

e32_emul1max

e64_emul1max

e16

e32

e64

e8_emul4max

e16_emul4max

cp_vl_0

Instruction

vssseg2e32.v

vssseg2e64.v

vssseg3e8.v

vssseg3e16.v

vssseg3e32.v

vssseg3e64.v

vssseg4e8.v

vssseg4e16.v

vssseg4e32.v

Type

VSXXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte30

lte29

lte28

cp_rs1

nx0

cp_rs2

cp_rs2_edges

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

cp_masking_edges

cr_vl_lmul

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

cr_vtype_agnostic

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

cp_vl_0

Instruction

vssseg4e64.v

vssseg5e8.v

vssseg5e16.v

vssseg5e32.v

vssseg5e64.v

vssseg6e8.v

vssseg6e16.v

vssseg6e32.v

vssseg6e64.v

Type

VSXXM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte28

lte27

lte26

cp_rs1

nx0

cp_rs2

cp_rs2_edges

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

cp_masking_edges

cr_vl_lmul

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

Instruction

vssseg7e8.v

vssseg7e16.v

vssseg7e32.v

vssseg7e64.v

vssseg8e8.v

vssseg8e16.v

vssseg8e32.v

vssseg8e64.v

vsuxei8.v

Type

VSXXM

VSXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte25

lte24

cp_vs2

cp_vs2_edges

cmp_vs3_vs2

cp_rs1

nx0

cp_rs2

cp_rs2_edges

ls_e8

ls_e16

ls_e32

ls_e64

ls_e8

ls_e16

ls_e32

ls_e64

cp_masking_edges

cr_vl_lmul

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

Instruction

vsuxei16.v

vsuxei32.v

vsuxei64.v

vsuxseg2ei8.v

vsuxseg2ei16.v

vsuxseg2ei32.v

vsuxseg2ei64.v

vsuxseg3ei8.v

vsuxseg3ei16.v

Type

VSXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte30

lte29

cp_vs2

cp_vs2_edges

cmp_vs3_vs2

lte30

lte29

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

cr_vtype_agnostic

e16

e32

e64

e8_emul4max

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

cp_vl_0

Instruction

vsuxseg3ei32.v

vsuxseg3ei64.v

vsuxseg4ei8.v

vsuxseg4ei16.v

vsuxseg4ei32.v

vsuxseg4ei64.v

vsuxseg5ei8.v

vsuxseg5ei16.v

vsuxseg5ei32.v

Type

VSXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte29

lte28

lte27

cp_vs2

cp_vs2_edges

cmp_vs3_vs2

lte29

lte28

lte27

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

cr_vtype_agnostic

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

cp_vl_0

Instruction

vsuxseg5ei64.v

vsuxseg6ei8.v

vsuxseg6ei16.v

vsuxseg6ei32.v

vsuxseg6ei64.v

vsuxseg7ei8.v

vsuxseg7ei16.v

vsuxseg7ei32.v

vsuxseg7ei64.v

Type

VSXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte27

lte26

lte25

cp_vs2

cp_vs2_edges

cmp_vs3_vs2

lte27

lte26

lte25

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

Instruction

vsuxseg8ei8.v

vsuxseg8ei16.v

vsuxseg8ei32.v

vsuxseg8ei64.v

vsoxei8.v

vsoxei16.v

vsoxei32.v

vsoxei64.v

vsoxseg2ei8.v

Type

VSXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte24

lte30

cp_vs2

cp_vs2_edges

cmp_vs3_vs2

lte24

lte30

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e16

e32

e64

e8_emul4max

cr_vtype_agnostic

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e16

e32

e64

e8_emul4max

cp_vl_0

Instruction

vsoxseg2ei16.v

vsoxseg2ei32.v

vsoxseg2ei64.v

vsoxseg3ei8.v

vsoxseg3ei16.v

vsoxseg3ei32.v

vsoxseg3ei64.v

vsoxseg4ei8.v

vsoxseg4ei16.v

Type

VSXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte30

lte29

lte28

cp_vs2

cp_vs2_edges

cmp_vs3_vs2

lte30

lte29

lte28

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

cr_vtype_agnostic

e16_emul4max

e32_emul4max

e64_emul4max

e8_emul2max

e16_emul2max

e32_emul2max

e64_emul2max

e8_emul2max

e16_emul2max

cp_vl_0

Instruction

vsoxseg4ei32.v

vsoxseg4ei64.v

vsoxseg5ei8.v

vsoxseg5ei16.v

vsoxseg5ei32.v

vsoxseg5ei64.v

vsoxseg6ei8.v

vsoxseg6ei16.v

vsoxseg6ei32.v

Type

VSXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte28

lte27

lte26

cp_vs2

cp_vs2_edges

cmp_vs3_vs2

lte28

lte27

lte26

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cr_vtype_agnostic

e32_emul2max

e64_emul2max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

cp_vl_0

Instruction

vsoxseg6ei64.v

vsoxseg7ei8.v

vsoxseg7ei16.v

vsoxseg7ei32.v

vsoxseg7ei64.v

vsoxseg8ei8.v

vsoxseg8ei16.v

vsoxseg8ei32.v

vsoxseg8ei64.v

Type

VSXVM

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vs3

lte26

lte25

lte24

cp_vs2

cp_vs2_edges

cmp_vs3_vs2

lte26

lte25

lte24

cp_rs1

nx0

cp_masking_edges

cr_vl_lmul

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cr_vtype_agnostic

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

e8_emul1max

e16_emul1max

e32_emul1max

e64_emul1max

cp_vl_0

Instruction

vl1re8.v

vl2re8.v

vl4re8.v

vl8re8.v

vl1re16.v

vl2re16.v

vl4re16.v

vl8re16.v

vl1re32.v

Type

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

emul4

emul8

emul2

emul4

emul8

cp_rs1

nx0

cr_vl_lmul

lmul4max

lmul2max

lmul1max

lmul4max

lmul2max

lmul1max

cr_vtype_agnostic

nomask

lmul4max_nomask

lmul2max_nomask

lmul1max_nomask

nomask

lmul4max_nomask

lmul2max_nomask

lmul1max_nomask

nomask

cp_vl_0

Instruction

vl2re32.v

vl4re32.v

vl8re32.v

vl1re64.v

vl2re64.v

vl4re64.v

vl8re64.v

vs1r.v

vs2r.v

Type

VSX

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

emul4

emul8

emul2

emul4

emul8

cp_vs3

emul2

cp_rs1

nx0

cr_vl_lmul

lmul4max

lmul2max

lmul1max

lmul4max

lmul2max

lmul1max

cr_vtype_agnostic

lmul4max_nomask

lmul2max_nomask

lmul1max_nomask

nomask

lmul4max_nomask

lmul2max_nomask

lmul1max_nomask

nomask

cp_vl_0

Instruction

vs4r.v

vs8r.v

vsm.v

vlm.v

Type

VSX

RV32

RV64

EFFEW8

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs3

emul4

emul8

cp_rs1

nx0

cr_vl_lmul

cr_vtype_agnostic

nomask

cp_vl_0

5.11.6. Vf

Table 72. Vf Instruction Coverpoints
Instruction	vfadd.vv	vfadd.vf	vfwadd.vv	vfwadd.vf	vfwadd.wv	vfwadd.wf	vfsub.vv	vfsub.vf	vfwsub.vv
Type	VVVM	VVFM	VVVM	VVFM	VVVM	VVFM	VVVM	VVFM	VVVM
RV32	x	x	x	x	x	x	x	x	x
RV64	x	x	x	x	x	x	x	x	x
EFFEW16	x	x	x	x	x	x	x	x	x
EFFEW32	x	x	x	x	x	x	x	x	x
EFFEW64	x	x					x	x
cp_asm_count	x	x	x	x	x	x	x	x	x
cp_vd	x	x	emul2	emul2	emul2	emul2	x	x	emul2
cp_vs2	x	x	x	x	emul2	emul2	x	x	x
cp_vs1	x		x		x		x		x
cp_fs1		x		x		x		x
cmp_vd_vs2	x	x			emul2	emul2	x	x
cmp_vd_vs1	x						x
cmp_vs1_vs2	x		x				x		x
cmp_vd_vs1_vs2	x						x
cp_vs2_edges	f	f	f	f	f_emul2	f_emul2	f	f	f
cp_vs1_edges	f		f		f		f		f
cr_vs2_vs1_edges	f		f		fwv		f		f
cp_fs1_edges		v		v		v		v
cr_vs2_fs1_edges		x		x		wf		x
cp_masking_edges	x	x	x	x	x	x	x	x	x
cr_vl_lmul	x	x	lmul4max	lmul4max	lmul4max	lmul4max	x	x	lmul4max
cr_vtype_agnostic	x	x	lmul4max	lmul4max	lmul4max	lmul4max	x	x	lmul4max
cp_vl_0	x	x	x	x	x	x	x	x	x
cp_csr_fflags	von	von	vn	vn	von	von	von	von	vn
cp_csr_frm	v	v	v	v	v	v	v	v	v

Instruction

vfwsub.vf

vfwsub.wv

vfwsub.wf

vfrsub.vf

vfmul.vv

vfmul.vf

vfwmul.vv

vfwmul.vf

vfdiv.vv

Type

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

emul2

cp_vs1

cp_fs1

cmp_vd_vs2

emul2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

f_emul2

cp_vs1_edges

cr_vs2_vs1_edges

fwv

cp_fs1_edges

cr_vs2_fs1_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_csr_fflags

von

voun

vun

vdoun

cp_csr_frm

Instruction

vfdiv.vf

vfrdiv.vf

vfmacc.vv

vfmacc.vf

vfnmacc.vv

vfnmacc.vf

vfmsac.vv

vfmsac.vf

vfnmsac.vv

Type

VVFM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_fs1

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_fs1_edges

cr_vs2_fs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_csr_fflags

vdoun

voun

cp_csr_frm

Instruction

vfnmsac.vf

vfmadd.vv

vfmadd.vf

vfnmadd.vv

vfnmadd.vf

vfmsub.vv

vfmsub.vf

vfnmsub.vv

vfnmsub.vf

Type

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_fs1

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_fs1_edges

cr_vs2_fs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_csr_fflags

voun

cp_csr_frm

Instruction

vfwmacc.vv

vfwmacc.vf

vfwnmacc.vv

vfwnmacc.vf

vfwmsac.vv

vfwmsac.vf

vfwnmsac.vv

vfwnmsac.vf

vfsqrt.v

Type

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVVMR

VFVM

VVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

cp_vs1

cp_fs1

cmp_vd_vs2

cmp_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_fs1_edges

cr_vs2_fs1_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_csr_fflags

vun

cp_csr_frm

Instruction

vfrsqrt7.v

vfrec7.v

vfmin.vv

vfmin.vf

vfmax.vv

vfmax.vf

vfsgnj.vv

vfsgnj.vf

vfsgnjn.vv

Type

VVM

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_fs1

cmp_vd_vs2

cmp_vd_vs1

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_fs1_edges

cr_vs2_fs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_csr_fflags

vdon

cp_csr_frm

Instruction

vfsgnjn.vf

vfsgnjx.vv

vfsgnjx.vf

vfredosum.vs

vfwredosum.vs

vfredusum.vs

vfwredusum.vs

vfredmax.vs

vfredmin.vs

Type

VVFM

VVVM

VVFM

VVVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

cp_vs1

emul2

cp_fs1

cmp_vd_vs2

cmp_vd_vs1

emul2

cmp_vs1_vs2

cmp_vd_vs1_vs2

cp_vs2_edges

cp_vs1_edges

f_emul2

cr_vs2_vs1_edges

fwred

cp_fs1_edges

cr_vs2_fs1_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_csr_fflags

von

cp_csr_frm

Instruction

vmfeq.vv

vmfeq.vf

vmfne.vv

vmfne.vf

vmflt.vv

vmflt.vf

vmfle.vv

vmfle.vf

vmfgt.vf

Type

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

VVVM

VVFM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

cp_vs1

cp_fs1

cmp_vs1_vs2

cp_vs2_edges

cp_vs1_edges

cr_vs2_vs1_edges

cp_fs1_edges

cr_vs2_fs1_edges

cp_masking_edges

cr_vl_lmul

cr_vtype_agnostic

cp_vl_0

cp_csr_fflags

Instruction

vmfge.vf

vfmerge.vfm

vfmv.v.f

vfmv.f.s

vfmv.s.f

vfslide1up.vf

vfslide1down.vf

vfcvt.xu.f.v

vfwcvt.xu.f.v

Type

VVFM

VVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

nv0

emul2

cp_fd

cp_vs2

nv0

cp_fs1

cmp_vd_vs2

nv0

cp_vs2_edges

cp_fs1_edges

cr_vs2_fs1_edges

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

nomask

lmul4max

cp_vl_0

cp_csr_fflags

cp_csr_frm

Instruction

vfncvt.xu.f.w

vfcvt.x.f.v

vfwcvt.x.f.v

vfncvt.x.f.w

vfcvt.rtz.xu.f.v

vfwcvt.rtz.xu.f.v

vfncvt.rtz.xu.f.w

vfcvt.rtz.x.f.v

vfwcvt.rtz.x.f.v

Type

VVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

emul2

cmp_vd_vs2

cp_vs2_edges

f_emul2

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_csr_fflags

cp_csr_frm

Instruction

vfncvt.rtz.x.f.w

vfcvt.f.xu.v

vfwcvt.f.xu.v

vfncvt.f.xu.w

vfcvt.f.x.v

vfwcvt.f.x.v

vfncvt.f.x.w

vfwcvt.f.f.v

vfncvt.f.f.w

Type

VVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

emul2

cp_vs2

emul2

cmp_vd_vs2

cp_vs2_edges

f_emul2

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_csr_fflags

voun

cp_csr_frm

Instruction

vfncvt.rod.f.f.w

vfclass.v

Type

VVM

RV32

RV64

EFFEW16

EFFEW32

EFFEW64

cp_asm_count

cp_vd

cp_vs2

emul2

cmp_vd_vs2

cp_vs2_edges

f_emul2

cp_masking_edges

cr_vl_lmul

lmul4max

cr_vtype_agnostic

lmul4max

cp_vl_0

cp_csr_fflags

voun

5.11.7. Zvfh Vector Half-Precision Floating-Point Extension

Half-precision vector floating-point is part of the Zvfh and Zvfhmin extensions, not the base V extension. Nevertheless, Zvfh tests are in the same directory structure as V, under Vf16. Zvfh uses Vf16 Table 72 to exercise all floating-point instructions with SEW=16.

5.11.8. Zvfhmin Half-Precision Conversions

Zvfhmin only exercises the widening and narrowing conversions: vfwcvt.f.f.v and vfncvt.f.f.w.

5.11.9. ZfaZvfh Half-Precision Load Immediate

When Zfa and Zvfh are both implemented, RISC-V provides a fli.h instruction (Table 74) even if full Zfh is not supported.

Table 74. ZfaZvfh Instruction Coverpoints
Instruction	fli.h
Type	FLI
RV32	x
RV64	x
cp_asm_count	x
cp_rs1	fli
cp_fd	x
cp_NaNBox	S_H
cp_fpr_hazard	w

5.11.10. Zvfbfmin BF16 Conversions

5.11.11. Zvfbfwma BF16 MAC

5.12. Zvb* Vector Bit Manipulation Extension

Vector bit manipulation extensions include Zvbb and Zvbc.

5.12.1. Zvbb Vector Basic Bit Manipulation Extension

5.12.2. Zvbc Vector Caryless Multiplication Extension

5.13. Zvk* Vector Cryptography Extension

There are several Zvk* vector cryptography extensions. Zvks ShangMi extensions are not yet supported.

5.13.1. Zvkb Vector Crypto Bit Manipulation Extension

5.13.2. Zvkg Vector Crypto Galois Field Extension

5.13.3. Zvkned Vector NIST Encryption and Decryption

5.13.4. Zvknh{a/b} Vector NIST Hashing

Table 82 lists the vector hashing instructions. These apply to both Zknha and Zknhb.

5.14. Miscellaneous RV23 Unprivileged Extensions

5.14.1. Zacas Atomic Compare and Swap

5.14.2. Zabha Subword Atomics

5.14.3. Zimop Maybe-Ops

Should write 0 to rd unless implemented.

5.14.4. Zcmop Compressed Maybe-Ops

Should write 0 to rd unless implemented.

5.15. Miscellaneous Non-RV23 Unprivileged Extensions

5.15.1. Zfinx Float in Integer Regs

Zfinx replaces the F extension with a similar set of instructions that operate on x registers instead of f registers. Zdinx and Zhinx are similar.

5.15.2. Zdinx Double in Integer Regs

5.15.3. Zhinx Half in Integer Regs

5.15.4. Zhinxmin Half Converts in Integer Regs

5.15.5. Zcmp Compressed Push/Pop

5.15.6. Zcmt Compressed Jump Tables

5.15.7. Zilsd Load/Store Double

5.15.8. Zclsd Compressed Load/Store Double

5.16. E Base Embedded Extension

The E extension is a variant of I with 16 general purpose registers. This test plan also includes tests restricted to these 16 registers for simple extensions most likely to be implemented on an enbedded core.

The test plans are identical to the integer equivalents. For example, E and I are the same, and EM is the same as M. The coverpoints and tests are almost identical but use 16 instead of 32 registers.

Table 95. E Normative Rules
Unpriv Section	Normative Rule	Coverpoints

E Instruction Coverpoints

See Table 10

5.16.1. EM Embedded + Multiply/Divide

EM Instruction Coverpoints

See Table 14

5.16.2. EZmmul Embedded + Multiply

See Table 16

5.16.3. EZca Embedded + Compressed

EZca Instruction Coverpoints

See Table 19

5.16.4. EZcb Embedded + More Compressed

EZcb Instruction Coverpoints

See Table 25

5.16.5. EZcmp Embedded + Compressed Push/Pop

EZcmp Instruction Coverpoints

See Table 91

5.16.6. EZcmt Embedded + Jump Tables

EZcmt Instruction Coverpoints

See Table 92

5.16.7. EZba Embedded + Address Generation

EZba Instruction Coverpoints

See Table 48

5.16.8. EZbb Embedded + Basic Bit Manipulation

EZbb Instruction Coverpoints

See Table 49

5.16.9. EZbs Embedded + Single-Bit Manipulation

EZbs Instruction Coverpoints

See Table 51

6. Privileged Test Plan

Privileged test plan spreadsheets are available. They need to be edited into a more standarized format. Each test plan spreadsheet contains multiple columns for the applicable configurations. For example, ZicsrM applies to any configuration with machine mode, ZicsrS applies to any configuration with supervisor mode, and ZicsrF applies to any configuration with floating-point.

Table 96. I Privileged Normative Rules
Unpriv Section	Normative Rule	Coverpoints
2.2	The base ISA has IALIGN=32, meaning that instructions must be aligned on a four-byte boundary in memory. An instruction-address-misaligned exception is generated on a taken branch or unconditional jump if the target address is not IALIGN-bit aligned. This exception is reported on the branch or jump instruction, not on the target instruction.
2.2	No instruction-address-misaligned exception is generated for a conditional branch that is not taken.
2.5	If an instruction access-fault or instruction page-fault exception occurs on the target of a jump or taken branch, the exception is reported on the target instruction, not on the jump or branch instruction.
2.5.1	The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary.
2.5.2	The conditional branch instructions will generate an instruction-address-misaligned exception if the target address is not aligned to a four-byte boundary and the branch condition evaluates to true.
2.5.2	If the branch condition evaluates to false, the instruction-address-misaligned exception will not be raised.
2.5.2	Loads with a destination of `x0` must still raise any exceptions and cause any other side effects even though the load value is discarded.
2.5.2	The EEI will define whether the memory system is little-endian or big-endian. In RISC-V, endianness is byte-address invariant.
2.6	Loads and stores whose effective address is not naturally aligned to the referenced datatype (i.e., the effective address is not divisible by the size of the access in bytes) have behavior dependent on the EEI.	* more in 2.6 spec
2.8	The `ECALL` instruction is used to make a service request to the execution environment.
2.8	The `EBREAK` instruction is used to return control to a debugging environment.

Table 97. C Privileged Normative Rules
Section	Normative Rule	Coverpoints
Unpriv 2.5.2	Instruction-address-misaligned exceptions are not possible on machines that support extensions with 16-bit aligned instructions, such as the compressed instruction-set extension, C.	*
Unpriv 27.1	With the addition of the C extension, no instructions can raise instruction-address-misaligned exceptions.	*
Unpriv 27.5.4	A 16-bit instruction with all bits zero is permanently reserved as an illegal instruction.	*
Unpriv 27.5.4	Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`, to cause control to be transferred back to the debugging environment. `C.EBREAK` shares the opcode with the `C.ADD` instruction, but with rd and rs2 both zero, thus can also use the `CR` format.	*
Unpriv 28.4	MISA.C is set if the following extensions are selected:	***read MISA

6.1. Privileged Instructions

The privileged testplan is organized by major categories of behaviors or extensions in the following sections. Each of these categories has multiple coverage files with suffixes indicating the circumstances to which they apply. For example, InterruptsM applies to any configuration with Zicsr and M-mode. InterruptsU applies to any configuration with Zicsr and U-mode. InterruptsS applies to any configuration with Zicsr and S-mode. S-mode implies the presence of U and M modes so all three coverage files apply to a system with S-mode. Moreover, InterruptsS includes tests that execute in U and M-mode, such as setting a bit in mideleg and then checking that the corresponding interrupt is delegated to S-mode when taken in U-mode, but not when taken in M-mode.

6.2. Zicsr

Zicsr privileged tests access to CSRs that are mandatory in each privilege mode. It also tests mandatory privileged instructions: ecall, ebreak, mret, and sret. The CSR read/write/set/clear instructions themselves are tested in the unprivileged Zicsr tests of Section 5.10.1.

wfi is tested in Section 6.4 and sfence.vma is tested in Section 6.10.

Zicsr does not test reserved or custom instructions or CSRs because their behavior is Unspecified. Reserved instructions and CSRs are tested in the Section 6.8 Ssstrict tests, where they should throw an Illegal Instruction exception if not implemented.

6.2.1. ZicsrM Machine-Mode CSRs

These test CSRs that exist in machine mode.

Google Sheet Testplan

find all WPRI and WLRL fields. Don’t look at WPRI results. Only test legal values of WLRL. TODO check WARL, WLRL, WPRI behaviors

6.2.2. ZicsrS Supervisor-Mode CSRs

These test additional CSRs that exist in supervisor mode.

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6.2.3. ZicsrU User-Mode CSRs

These test additional CSRs that exist in user mode.

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6.2.4. ZicsrF Floating-Point CSRs

These test additional CSRs that exist when floating-point is supported.

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6.2.5. ZicsrV Vector CSRs

These test additional CSRs that exist when vector is supported.

need link

6.2.6. ZicsrUF Unprivileged Floating-Point CSRs

These test additional CSR scenarios that exist when floating-point and user mode are supported.

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6.2.7. ZicsrUV Unprivileged Vector CSRs

These test additional CSR scenarios that exist when vector and user mode are supported.

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6.2.8. ZicsrZkr Entropy CSR

These test CSRs when the Zkr entropy extension is supported.

6.3. Exceptions

Exception tests are organized according to the privilege mode or extension supported. For example, a configuration with Machine, Supervisor, User, and Floating-Point supported should run ExceptionsM, ExceptionsS, ExceptionsU, and ExceptionsF.

6.3.1. ExceptionsM Machine-Mode Exceptions

These tests are run on any configuration with machine mode that supports exceptions.

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6.3.2. ExceptionsS Supervisor-Mode Exceptions

These additional exception tests are run on configurations with supervisor mode.

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6.3.3. ExceptionsU User-Mode Exceptions

These additional exception tests are run on configurations with user mode.

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6.3.4. ExceptionsF Floating-Point Exceptions

These additional exception tests are run on configurations with floating-point (at least the F extension).

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6.3.5. ExceptionsV Vector Exceptions

These additional exception tests are run on configurations with vector (V extension or subsets thereof that rely on mstatus.VS).

add link

6.3.6. ExceptionsZalrsc Atomic LR/SC Exceptions

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6.3.7. ExceptionsZaamo Atomic Memory Operation Exceptions

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6.3.8. ExceptionsZc Compressed Instruction Exceptions

These additional exception tests are run on configurations with compressed instructions (C, Zca, Zcb, etc.). They attempt to test all compressed loads and stores, but may throw an illegal instruction fault on compressed subword load/store if Zcb is not supported.

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6.3.9. ExceptionsZicboS Supervisor-Mode CBO Exceptions

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6.3.10. ExceptionsZicboU User-Mode CBO Exceptions

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6.3.11. ExceptionsVM Virtual Memory Exceptions

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6.3.12. ExceptionsVMZalrsc Virtual Memory LR/SC Exceptions

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6.3.13. ExceptionsVMZaamo Virtual Memory AMO Exceptions

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6.3.14. Zicclsm Misaligned Loads/Stores

Misaligned loads/stores handled in hardware.

need to create this

6.4. Interrupts

Interrupt tests are organized according to the privilege mode or extension supported.

6.4.1. InterruptsM Machine-Mode Interrupts

These tests are run on any configuration with machine mode that supports interrupts.

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6.4.2. InterruptsS Supervisor-Mode Interrupts

These tests are run on any configuration with supervisor mode that supports interrupts. Note that they include tests in other modes, such as interrupts from user mode delegated to supervisor mode.

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6.4.3. InterruptsU User-Mode Interrupts

These tests are run on any configuration with user mode that supports interrupts.

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6.4.4. InterruptsSstc Supervisor Timer Compare Interrupts

These tests are run when the Sstc supervisor timer compare extension is supported.

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6.5. Zicntr

These tests exercise the mtime, mcycle, and minstret counters and related registers (time, cycle, instret).

edit coverpoints to pull out hpm

6.5.1. ZicntrM Machine-Mode Counters

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6.5.2. ZicntrS Supervisor-Mode Counters

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6.5.3. ZicntrU User-Mode Counters

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6.6. Zihpm Hardware Performance Monitors

These tests exercise the custom hardware performance monitor CSRs. Their behavior is user-defined, so these tests just check that the set of writable bits match the reference model.

Zicntr checks how {m/s}counteren controls access to counters and hpms at lower privilege levels, so there is no need to check across privilege levels.

6.7. Endian

6.7.1. EndianM Machine-Mode Endianness

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6.7.2. EndianS Supervisor-Mode Endianness

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6.7.3. EndianU User-Mode Endianness

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6.7.4. EndianZaamo Endianness for AMOs

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6.7.5. EndianZalrsc Endianness for LR/SC

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6.8. Ssstrict

The Ssstrict extension indicates that executing unimplemented instructions or accessing unimplemented CSR in the standard or reserved encoding spaces raises an illegal instruction exception.

No non-conforming extensions are present. Attempts to execute unimplemented opcodes or access unimplemented CSRs in the standard or reserved encoding spaces raises an illegal instruction exception that results in a contained trap to the supervisor-mode trap handler.

6.8.1. SsstrictM

RISC-V does not have a ratified equivalent of Ssstrict for machine mode, but this optional test suite checks the behavior of unimplemented instructions and CSRs from machine mode.

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6.8.2. SsstrictS

Attempt to issue all flavors of 32-bit instructions in the standard and reserved spaces and all 16-bit compressed instructions. Also attempt to access all CSRs in the standard and reserved spaces. Expect illegal instruction trap for unimplemented instructions and CSRs, matching reference model.

According to the RVA23 profile spec, the illegal instruction should be cause a trap to the supervisor trap handler. However, delegation is the business of the firmware, not the hardware. These tests only check that a trap occurs and matches the reference model.

for all mention of reserved in Zca, list normative rule here and give coverpoint

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6.8.3. SsstrictV

Test that all behaviors called out as "reserved" in the vector specification cause an illegal instruction fault. Required when Ssstrict and V are both present.

need link

6.9. PMP

6.9.1. PMPM

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6.9.2. PMPS

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6.9.3. PMPU

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6.9.4. PMPF

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6.9.5. PMPZca

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6.9.6. PMPZicbo

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6.9.7. PMPZaamo

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6.9.8. PMPZalrsc

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6.10. Sv* Virtual Memory

6.10.1. Svbare Virtual Memory Off

6.10.2. Sv

config file determines whether to run SV32/39/48/57

6.10.3. VMPMP VM + PMP

6.10.4. VMZicbo VM + CBOM/CBOZ

config file determines whether to run cbom/cboz/both .VMZicbo Coverpoints

6.10.5. VMPMPZicbo VM + PMP + CBOM/CBOZ

config file determines whether to run cbom/cboz/both

6.10.6. Svinval Memory Management Unit Table Invalidation

The Svinval extension defines instructions to update memory management tables for virtual memory and optionally for PMP. Their effect is system-dependent, so these tests simply check that the instructions run.

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6.10.7. Svade A/D Bit Page Fault Exception

6.10.8. Svadu A/D Bit Hardware Update

6.10.9. Svpbmt Page-Based Memory Types

6.10.10. Svnapot Naturally-Aligned Power-of-Two Page Sizes

6.11. H Hypervisor

The Hypervisor Extension adds an H coverage file containing new Hypervisor instructions, and additional coverage files related to exceptions, interrupts, endian, and virtual memory.

6.11.1. H Hypervisor Instructions

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6.11.2. ZicsrH Hypervisor CSRs

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6.11.3. ExceptionsH Hypervisor Exceptions

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6.11.4. ExceptionsHV Hypervisor Vector Exceptions

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6.11.5. InterruptsH Hypervisor Interrupts

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6.11.6. EndianH Hypervisor Endianness

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6.11.7. ZicntrH Hypervisor Counters

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ZicntrH exercises hcounteren for all 32 counters, so no separate ZihpmH suite is needed.

6.11.8. PMPH Hypervisor Physical Memory Protection

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6.11.9. RV32VMH Hypervisor 2-Stage Virtual Memory

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6.11.10. RV32VMH_CBO Hypervisor VM + Cache Block Operations

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6.11.11. RV64VMH Hypervisor 2-Stage Virtual Memory

Virtual memory behavior introduced by Hypervisor extension.

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6.11.12. RV64VMH_CBO Hypervisor VM + Cache Block Operations

Virtual memory / CBO behavior introduced by Hypervisor extension.

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6.11.13. Shcounterenw Writable Counter Enables

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6.11.14. Shvsatpa Virtual Memory Modes Supported

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6.11.15. Shgatpa Virtual Memory x4 Modes Supported

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6.11.16. Shvstvecd VS-Mode Direct Vectors

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6.11.17. Shvstvala VS-Mode Trap Address

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6.11.18. Shtvala HS-Mode Trap Address

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6.11.19. Shlcofideleg Hypervisor Counter Overflow Delegation

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6.11.20. ZkrH Hypervisor Entropy Register

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6.11.21. SstcH Hypervisor Timer Compare

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6.11.22. SsstateenH Hypervisor State Enable

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6.11.23. SscrindH Hypervisor Indirect CSR Access

Hypervisor indirect CSR access.

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6.11.24. SscfgH Hypervisor Counter Delegation

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6.11.25. SmctrH Hypervisor Control Transfer Records

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6.11.26. SvinvalH Hypervisor Memory Management Table Invalidation

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6.11.27. SvaduH Hypervisor Hardware Page Table A/D Updates

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6.11.28. ZicfilpH Hypervisor Landing Pads

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6.11.29. ZicfissH Hypervisor Shadow Stack

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6.11.30. SsdbltrpH Hypervisor Double Trap

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6.11.31. SsnpmH Hypervisor Pointer Masking

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6.11.32. SmnpmH Hypervisor Pointer Masking

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6.12. Miscellaneous RV23 Privileged Extensions

6.12.1. Sscofpmf Counter filtering

6.12.2. Ssstateen Supervisor State Enable

6.12.3. Ssu64xl 64-bit User Mode

RV64 only

6.12.4. Sscounterenw Writable Counter Enables

6.12.5. Sstvecd Direct Trap Vector

6.12.6. Sstvala Trap Address

6.12.7. Ss1p13 Supervisor Mode 1.13

6.12.8. Ssnpm Pointer Masking

6.12.9. Smnpm Pointer Masking

6.12.10. Smmpm Pointer Masking

6.12.11. Zicfilp Landing Pads

In Privileged section because it has both unpriv and privileged behaviors.

6.12.12. Zicfiss Shadow Stack

In Privileged section because it has both unpriv and privileged behaviors.

6.12.13. Zawrs Wait on Reservation Set

Waits until timeout on a single hart that cannot modify the reservation set.

6.12.14. Sdtrig Debug Triggers

Located here because it is part of RVA23 even though it is not very interesting without the Sdext debug extension.

also check the value written to stval and vstval. Should be the VA of the breakpoint when Sstvala and Shvstvala are supported. This is automatically checked against the reference model, so there is no need for additional SdtrigSstvala and SdtrigShvstvala test suites.

6.13. Miscellaneous Non-RV23 Privileged Extensions

6.13.1. Sm1p13 Machine Mode 1.13

6.13.2. Smstateen Machine State Enable

6.13.3. Smcsrind Machine-Mode Indirect CSR Access

6.13.4. Sscsrind Supervisor-Mode Indirect CSR Access

6.13.5. Smepmp Enhanced PMP

6.13.6. Smrnmi Machine-Mode Resumable Non-Maskable Interrupts

6.13.7. Ssrnmi Supervisor-Mode Resumable Non-Maskable Interrupts

6.13.8. Smcntrpmf Counter Privilege Mode Filtering

6.13.9. Smcdeleg Counter Delegation

6.13.10. Ssccfg Counter Delegation

6.13.11. Smdbltrp Machine Double Traps

6.13.12. Ssdbltrp Supervisor Double Traps

6.13.13. Smctr Control Transer Records

6.13.14. Ssqosid Quality-of-Service ID

7. Non-ISA Test Plan

This chapter contains test plans for ratified RISC-V non-ISA features.

7.1. Debug

This section describes debug-related extensions not required in RVA23.

7.1.1. DM Debug Module

7.1.2. DTM Debug Transport Module

7.1.3. Sdext Debug Extension

7.2. AIA Advanced Interrupt Architecture

This section describes AIA extension test plans.

7.2.1. Smaia Machine-Mode Advanced Interrupt Architecture

7.2.2. Ssaia Supervisor-Mode Advanced Interrupt Architecture

7.2.3. IMSIC Incoming MSI Controller

7.2.4. APLIC Advanced Platform-Level Interrupt Controller

7.2.5. IOMMU I/O Memory Management Unit

8. Trick Box

Each DUT requires a trick box to perform the following non-ISA functions:

Run DUT-specific boot code
Deliver each supported type of interrupt to the core (Machine/Supervisor External/Timer/Software + guest external interrupts)
Send a character to a terminal to log a success message or test failure information
Terminate a test
If a debug module is supported, send commands to the DM

8.1. Trick Box Macros

The trick box is implemented with DUT-specific macros in given in Table 221.

Table 221. Trick Box Macros
Macro	Description
RVMODEL_BOOT	Perform boot operations, such as turning on a phase-locked loop or DRAM controller
RVMODEL_HALT	Terminate test. When the test is run in simulation, this should end the simulation.
RVMODEL_IO_INIT	Initialization steps needed prior to writing to the console
RVMODEL_IO_WRITE_STR(_R, _STR)	Write a null-terminated ASCII string to the console, where _R * and _STR *
RVMODE_SET_MEXT_INT	Sets the Machine External Interrupt (mip.MEIP = 1, if supported)
RVMODEL_CLR_MEXT_INT	Clears the Machine External Interrupt (mip.MEIP = 0)
RVMODEL_SET_MTIMER_INT	Sets the Machine Timer Interrupt (mip.MTIP = 1, if supported)
RVMODEL_CLR_MTIMER_INT	Clears the Machine Timer Interrupt (mip.MTIP = 0)
RVMODEL_SET_MTIMER_INT_SOON	Cause the Machine Timer Interrupt to rise soon, but not immediately. This is used to check that an interrupt can fire in the future, such as for WFI. A delay of about 100 cycles is typically adequate to run a small amount of code after this macro.
RVMODEL_SET_MSW_INT	Sets the Machine Software Interrupt (mip.MSIP = 1)
RVMODEL_CLR_MSW_INT	Clears the Machine Software Interrupt (mip.MSIP = 0)
RVMODEL_SET_SEXT_INT	Sets the Supervisor External Interrupt (sip.SEIP = 1, if supported)
RVMODEL_CLR_SEXT_INT	Clears the Supervisor External Interrupt (sip.SEIP = 0)
RVMODEL_SET_STIMER_INT	Sets the Supervisor Timer Interrupt (sip.STIP = 1, if supported)
RVMODEL_CLR_STIMER_INT	Clears the Supervisor Timer Interrupt (sip.STIP = 0)\
RVMODEL_SET_STIMER_INT_SOON	Cause the Supervisor Timer Interrupt to rise soon, but not immediately.
RVMODEL_SET_SSW_INT	Sets the Supervisor Software Interrupt (mip.SSIP = 1, if supported)
RVMODEL_CLR_SSW_INT	Clears the Supervisor Software Interrupt (mip.SSIP = 0)
RVMODEL_WRITE_GEIP(_R)	Write the value in _R to the Guext External Interrupt Pending (hgeip) register, if supported. This is used to test guest external interrupts. Only the bottom GEILEN bits are written.
ACCESS_FAULT_ADDRESS	An address that causes an access fault when read or written. This is used to test exceptions.

way to send success/fail code when terminating sim
is STIMER_INT_SOON necessary?

The macros are defined in . shows sample implementations of these macros compatible with Spike.

8.2. Linker Script

8.3. Reference Trick Box for Spike and SAIL

github.com/openhwgroup/cvw/blob/main/tests/riscof/sail_cSim/env/model_test.h shows a trick box implementation that works for Spike and SAIL.

HTIF (write_tohost followed by j to selfloop) for termination and UART, memory-mapped PLIC and CLINT
not implemented yet on Sail

8.4. Host Target Interface

minimally documented (see ch 3) Ways to terminate (success or failure) and write a character Drawback that testbench must parse the ELF labels to find the address of write_tohost

8.5. Custom Trick Box Hints

For a simple design, the easiest way to support tests may be to emulate the capabilities of the Spike UART. * example

A commercial design will have its own peripherals including interrupt controller and UART, and will need to implement the trick box macros to use those peripherals. Typical trick box macros may do the following:

9. Architectural Functional Coverage

In principle, a test plan could simply list a set of features to test, and a set of tests that exercise these features. Experienced verification engineers have learned that tests often have bugs and don’t exercise the feature that the author intended. Many of these bugs can be caught if a different engineer independently writes functional coverpoints that measure whether the tests exercised the features.

This Certification Test Plan focuses on whether a DUT implements all of the architectural features of a profile. Architectural features are those that are directly visible to the programmer, especially those defined in the unprivileged and privileged ISA specifications.

Later phases of certification tests may add ratified architectural features outside the ISA spec, such as IOMMU, debug, or AIA.

Certification differs from design verification in that it does not systematically test microarchitectural features. Design verification must be aware of DUT-specific features such as the pipeline design. For example, DV should test design-specific interactions of interrupt arrival time, pipeline hazards, multicycle instructions, MMU, and memory system. Design verification also should test tricky implementation issues, such as hard floating-point rounding cases.

This plan uses the term Architectural Functional Coverage to describe the functional coverpoints required for certification. In contrast, full design verification also has Microarchitectural Functional Coverage.

Functional coverage also differs from code coverage, which measures whether the test suite exercises all of the lines of code in the RTL. Each of these detects different types of bugs. Code coverage is part of DV but not certification.

Architectural functional coverage requires a way to measure the architectural state of the machine after each instruction. The RISC-V Verification Interface (RVVI) provides a standard way to observe this state in the DUT. This document defines Extended RVVI with additional signals to facilitate testing virtual memory.

links to unpriv and priv specs

9.1. Extended RVVI

As compared to the base RVVI, Extended RVVI adds the following signals:

Table 222. Extended RVVI Signals
Signal	Width	Description
virt_adr_i	XLEN	Virtual address of instruction
virt_adr_d	XLEN	Virtual address of data accessed by instruction
phys_adr_i	PA_BITS	Physical address of instruction
phys_adr_d	PA_BITS	Physical address of data accessed by instruction
pte_i	XLEN	Instruction page table entry
pte_d	XLEN	Data page table entry
ppn_i	PPN_BITS	Instruction physical page number
ppn_d	PPN_BITS	Data physical page number
page_type_i	2	Instruction page type ***explain
page_type_d	2	Data page type
read_access	1	Instruction reads data (loads, AMOs, ***CMO)
write_access	1	Instruction writes data (stores, AMO, ***cbo.zero)
execute_access	1	***define - is this jumps? when asserted, and does it only affect data accesses?

PA_BITS PPN_BITS = PA_BITS - 12
why do we need ppn when we have phys_addr? Why not derive locally?
do we need to add guest physical address? Such as
- gpa_adr_i
- gpa_adr_d

maybe guest page table entries?

9.2. riscvISACOV Signals

Coverpoints are described using the open riscvISACOV framework.

The framework collects data coming across the RVVI interface and presents it with ins.current and ins.prev data structures to allow easy access to the architectural state at the end of the current and previous instructions. For example, ins.current.rs1 is the source register for the current instruction, and ins.current.rd_val is the value written to the destination register by the current instruction.

Most coverpoints use ins.current, to measure architectural state at the end of the instruction. However, some privileged coverpoints need to know the privilege mode or values of CSRs at the start of the instruction and thus use ins.prev.

The available fields are given in fcov/coverage/RISCV_coverage_rvvi.svh. Most commonly used fields are summarized in Table 223. Other fields include floating-point and vector register IDs and values, MMU extended RVVI signals, vector type information, and pending interrupts.

Table 223. riscvISACOV Signals for Coverpoints
Signal	Width	Description	Example
insn	ILEN	Instruction bit pattern	* add x10, x11, x12
inst_name	string	Instruction name	add
disass	string	Disassembled instruction	`add x10, x11, x12`
trap	1	Instruction trapped rather than retiring	0
mode	2	Privilege mode 11 = machine, 01 = supervisor, 00 = user	11
pc_rdata	XLEN	PC of current instruction	0x80000000
pc_wdata	XLEN	PC of next instruction	0x80000004
rs1	5	Source register 1 ID	11
rs2	5	Source register 2 ID	12
rd	5	Destination register ID	10
rs1_val	XLEN	Source register 1 value	42
rs2_val	XLEN	Source register 2 value	69
rd_val	XLEN	Value written to destination register	111
imm	XLEN	Value of immediate	100
csr	XLEN x 4096	Value of CSRs

exact meaning of trap, importance in writing test
do we need pending interrupts, or can this be part of mip?

RVVI and riscvISACOV support the notion of multiple harts that retire multiple instructions per cycle. The number of instructions retired per cycle is a microarchitectural issue irrelevant to architectural functional verification, so it is set to 1, consistent with simulators that report each instruction retiring individually. Phase 0-2 testing only involves a single hart. Later phases may need to generalize to multiple harts to exercise fences and atomic operations that relate to memory consistency.

Our riscvISACOV implementation uses a SystemVerilog disassmbler in fcov/disassemble.svh, replacing a proprietery disassembler from Imperas. When adding new extensions, update the disassembler accordingly.

9.3. Writing Coverpoints with riscvISACOV

example of coverpoint
organization of files

9.4. Sail Trace Coverage Flow

Coverage is measured by running tests on Sail and generating a RVVI-Trace file, then passing this file to an RVVI agent in a SystemVerilog testbench that checks coverage.

The number of coverpoints and the number of tests both grow with the number of extensions, so the runtime to measure coverage can grow quadratically with the number of extensions, and becomes problematic. To avoid this, it is recommended to only enable coverpoints for one extension (or small group of extensions) at a time and to only run tests for that extension, and generate a Unified Coverage Database (UDCB) file and report for that extension. A script will kick off such tests in parallel for all extensions, and merge the coverage reports.

Sail produces the trace file in a standard RVVI-Trace format (see Section Section 9.5). Any other simulator that implements the same trace format can also be used to cross-check coverage.

Jordan add instructions on how to run this

9.5. RVVI-Trace Format

Jordan write
how to handle instructions that change multiple CSRs, such as a write to mstatus.SIE also affecting sstatus.SIE

10. Reference Model

Certification relies on a reference model (simulator) to compute the expected results of a test, such as sum of two numbers in an add instruction or the answer for a fsqrt.d instruction. Self-checking tests compare the result from the DUT against the expected result that was precomputed by the reference model and flag mismatches.

RISC-V International has blessed Sail as the golden RISC-V model, so Sail is used as the reference model.

10.1. Deterministic, Nondeterministic, and Unspecified Behaviors

RISC-V feature behavior can be classified as deterministic, nondeterministic, and unspecified. Determinstic features have a unique expected value for a given configuration, such as the result of sub 1 - 2 on RV32. Nondetermistic features have a fine set of possible outcomes, and might vary unpredictably even on the same DUT. For example, vector tail-agnostic elements can preserve the input value or propagate all 1s, with no guarantee whether the same instruction has the same behavior on all elements or when executed twice in a row. Unspecifed features, such as unimplemented instructions, could do anything, from being ignored, to preditably or unpredictably changing architectural state, to halting and catching fire.

All RISC-V simulators, when properly configured to match the behavior of a DUT, should produce the same answers as the DUT and each other for deterministic features. For nondeterministic features, they should produce one of the legal outcomes. For unspecified features, they can do anthing.

Self-checking certification tests must check that the resut of deterministic features match the reference model. Nondeterministic features must produce one of the finite set of legal outcomes, which must be provided by the test developer because a reference model only produces a single outcome. Unspecified features are not tested because there are no wrong answers.

This is harder than it seems because RISC-V has many features whose behaviors are not fully specified. Many of these features are not yet named, and the set of legal behaviors is not yet enumerated. Unified Database (UDB) is in the process of naming and enumerating all of these features and behaviors to fully describe the behavior of a DUT. Moreover, no simulator yet is fully configurable to match every feature. Some simulators, such as Spike, intentionally have a minimal set of configuration options and are hardwired to particular behaviors.

Nevertheless, Sail is making rapid progress and is aiming to fully implement the ratified RVA23 profile, read a UDB configruation, and support at least the most reasonable behaviors in time for certification.

10.2. Test Qualification

For each supported profile, the certification tests will be qualified on at least one DUT configuration. This configuration should be one supported by Spike and as many other simulators as possible. Qualification involves running the same compiled tests on many RISC-V simulators and having them all pass. Preferred simulators include:

Sail (required, golden reference)
Spike
ImperasFPM (license required)
QEMU
Whisper
IDL (if available)

The configuration includes

Memory map and linker with main memory starting at 0x80000000
Reset vector at 0x80000000, or at 0x1000 with a jump to 0x80000000 before any tests are run
Trick box including:
- CLINT configured at 0x***
- * TBD how to trigger external interrupts & HGEI
- RVMODEL_HALT using HTIF write_tohost followed by a infinite loop jump to self
- Empty RVMODEL_BOOT macro (no boot code required)
  - will describe such UDB configurations for each certification profile.

Tests can receive a qualification waiver if they fail in certain simulators for the following reasons:

The simulator does not yet support the relevant extension
The simulator has a known bug with an issue filed
The simulator cannot be configured for a feature in a way compatible with the set of configurations supported by Sail and Spike

10.3. List of Fundamentally Nondeterministic Behaviors

Mask- and tail-agnostic vector operations
- Self-checking tests must accept undisturbed and all 1s in each element
Traps on misaligned accesses
- If mtval is written with a nonzero value, it can be any address within the access***
- When it also causes access fault, Allen has list of 7ish possible outcomes.
  - need to identify all coverpoints whose behavior is nondetermistic, and list all acceptable test outcomes as part of the test spec.

10.4. List of Theoretically Nondeterministic Behaviors with Configurable Deterministic Implementations

CSR WARL Fields: any legal value could be read, and the value is theoretically nondeterministic and could change from one write to another. UDB will define configurations with a single sensible behavior (such as all 0s), and we may limit certification to DUTs that implement a reasonable configuration.

11. Framework

The Certification Framework is the tool to:

select the appropriate tests for the DUT configuration
build these tests for the DUT
generate expected values specific to the DUT configuration parameters, using the reference model
rebuild the tests in self-checking form
check log files to confirm all required tests ran successfully on the DUT

The framework also provides developer tools to check that the tests hit 100% of the coverpoints, and to run the tests on multiple simulators to check for consistency.

The user is responsible for providing the DUT, including a testbench that can read an ELF file, run it on the DUT, and save console output to a log file. The DUT could be an RTL model, or it could be silicon connected to memories and a serial console. The user is also responsible for scripting that launches tests for all self-checking ELF files in a hierarchical directory. For a nontrivial RTL model, this generally is done in parallel on a server or compute farm.

riscof

11.1. Using the Framework

update all of this when it is ready

To use the Certification Framework:

1) Clone the certification repository

git clone https://github.com/riscv-non-isa/riscv-arch-test

2) Change into the directory

cd riscv-arch-test

3) Write your UDB configuration YAML for your DUT

See framework/examples/wally_rv64gc/udb.yaml for an example of an RVA22S64 profile
directions to configuration options
where to put it

4) Implement the trick box macros for your DUT

See framework/examples/wally_rv64gc/model_test.h for a trick box See Section 8.5 for hints about customizing the trick box to your DUT.

5) Run the framework to produce ELFs for your DUT

riscof run --config framework/examples/wally_rv64gc/udb.yaml

Checks consistency of configuration
Uses UDB to generate tools-specific configurations and build scripts
Describe output file directories

6) Run the ELFs for your DUT on your testbench and produce log files

7) Run the framework to check that all required tests completed and passed

riscof check --log ***

If all tests passed, you should see:

Certification Successful: xxx test files passed

8) Optional: confirm that the tests hit all of the coverpoints

riscof coverage ***

9) Optional: run the tests on other simulators.

riscof sim spike --configdir *** --elfdir ***
riscof sim qemu --configdir *** --elfdir ***
riscof sim whisper --configdir *** --elfdir ***
riscof sim imperasfpm --configdir *** --elfdir ***
riscof sim idl --configdir *** --elfdir ***

11.2. Test Regression

RISC-V is highly configurable, and there is a need to check that the coverpoints and tests work with all certifiable configurations. Moreover, the spec, reference model, compiler, and other components are rapidly evolving, so the test plan is susceptible to bitrot, ceasing to run.

The framework also must provide a CTP regression feature. It builds and runs all of the applicable tests on each profile nightly, looking for failures or coverage holes. It also generates a wide range of UDB configurations that vary the values of supported parameters. It identifies the tests that are impacted by these parameters, and runs them in the nightly regression.

TO DO: define fully configured baseline configs, supported parameters

12. To Do

I think we might want to rethink some of our privileged testing structure and switch to having Sm, S, and U testplans/coverpoints/tests instead of lumping most of that into ZicsrM/S/U. I will also be more apparent what is being tested where that way.

12.1. Current Status

At present, coverpoints and tests are being developed in the cvw-arch-verif repository and being tested on the CORE-V Wally processor. The goal is to be able to certify RVA23S64 as well as spec-compliant machine mode.

This test plan exists in the form of spreadsheets, and is being converted to ASCII Doc.

As of July 2025, all unprivileged and privileged RVA23S64 features have tests hitting 100% of the coverpoints, with the following exceptions:

The Vector tests found some bugs in Sail, which are being fixed
Interrupt tests coverpoints complete, tests partially complete
PMP tests in progress
Virtual memory: Sv39 and Sv48 100% coverage, Sv48 debugging one coverpoint
Hypervisor not started
Other minor new extensions not started

Appendix A: Examples

This appendix gives examples of coverpoints and tests consistent with the test plan. These examples are not the only way to satisfy the testplan.

A.1. Unprivileged example: `add`

Coverage is in I_coverage.svh:

Listing 2. add Covergroup

covergroup I_add_cg with function sample(ins_t ins);
    option.per_instance = 0;
    cp_asm_count : coverpoint ins.ins_str == "add"  iff (ins.trap == 0 )  {
        //Number of times instruction is executed
        bins count[]  = {1};
    }
    cp_rs1 : coverpoint ins.get_gpr_reg(ins.current.rs1)  iff (ins.trap == 0 )  {
        //RS1 register assignment
    }
    cp_rs2 : coverpoint ins.get_gpr_reg(ins.current.rs2)  iff (ins.trap == 0 )  {
        //RS2 register assignment
    }
    cp_rd : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.trap == 0 )  {
        //RD register assignment
    }
    cp_rs1_edges : coverpoint unsigned'(ins.current.rs1_val)  iff (ins.trap == 0 )  {
        `ifdef XLEN32
            bins zero  =    {0};
            bins one  =     {32'b00000000000000000000000000000001};
            bins two  =     {32'b00000000000000000000000000000010};
            bins min  =     {32'b10000000000000000000000000000000};
            bins minp1  =   {32'b10000000000000000000000000000001};
            bins max  =     {32'b01111111111111111111111111111111};
            bins maxm1  =   {32'b01111111111111111111111111111110};
            bins ones  =    {32'b11111111111111111111111111111111};
            bins onesm1  =  {32'b11111111111111111111111111111110};
            bins walkeodd = {32'b10101010101010101010101010101010};
            bins walkeven = {32'b01010101010101010101010101010101};
            wildcard bins random = {32'b01???????????????????????????010};
        `else
            bins zero  = {0};
            bins one      = {64'b0000000000000000000000000000000000000000000000000000000000000001};
            bins two      = {64'b0000000000000000000000000000000000000000000000000000000000000010};
            bins min      = {64'b1000000000000000000000000000000000000000000000000000000000000000};
            bins minp1    = {64'b1000000000000000000000000000000000000000000000000000000000000001};
            bins Wmax     = {64'b0000000000000000000000000000000011111111111111111111111111111111};
            bins Wmaxm1   = {64'b0000000000000000000000000000000011111111111111111111111111111110};
            bins Wmaxp1   = {64'b0000000000000000000000000000000100000000000000000000000000000000};
            bins Wmaxp2   = {64'b0000000000000000000000000000000100000000000000000000000000000001};
            bins max      = {64'b0111111111111111111111111111111111111111111111111111111111111111};
            bins maxm1    = {64'b0111111111111111111111111111111111111111111111111111111111111110};
            bins ones     = {64'b1111111111111111111111111111111111111111111111111111111111111111};
            bins onesm1   = {64'b1111111111111111111111111111111111111111111111111111111111111110};
            bins walkeodd = {64'b1010101010101010101010101010101010101010101010101010101010101010};
            bins walkeven = {64'b0101010101010101010101010101010101010101010101010101010101010101};
            wildcard bins random = {64'b01???????????????????????????????????????????????????????????010};
        `endif
    }
    cp_rs2_edges : coverpoint unsigned'(ins.current.rs2_val)  iff (ins.trap == 0 )  {
        `ifdef XLEN32
            bins zero  =    {0};
 ...
        `else
            bins zero  = {0};
            ...
        `endif
    }
    cr_rs1_rs2_edges : cross cp_rs1_edges,cp_rs2_edges  iff (ins.trap == 0 )  {
        //Cross coverage of RS1 edges and RS2 edges
    }
    cmp_rs1_rs2 : coverpoint ins.get_gpr_reg(ins.current.rs1)  iff (ins.current.rs1 == ins.current.rs2 & ins.trap == 0 )  {
        //Compare assignments of all registers
    }
    cmp_rd_rs1 : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs1 & ins.trap == 0 )  {
        //Compare assignments of all registers
    }
    cmp_rd_rs2 : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
        //Compare assignments of all registers
    }
    cmp_rd_rs1_rs2 : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs1 & ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
        //Compare assignments of all registers
    }
    cp_gpr_hazard_rw : coverpoint check_gpr_hazards(ins.hart, ins.issue)  iff (ins.trap == 0 )  {
        //GPR Hazard
        bins hazards[]  = {NO_HAZARD, RAW_HAZARD, WAW_HAZARD, WAR_HAZARD};
    }
endgroup

Corresponding RV32 tests are in tests/rv32/I/I-add.S. Observe how the directed tests align with the coverpoints and bins. Register numbers and values are randomized unless they are swept by the coverpoint. The RVTEST_SIGUPD macro compares the result against an expected signature produced by a reference model. When register 0 is used, it is loaded with a random value, but hardwired to 0, so the reference model will show that it behaves as 0.

Listing 3. add Tests

# Testcase cp_rs1 (Test source rs1 = x0)
li x0, 0xb4e96718 # initialize rs1
li x24, 0xeaa512b3 # initialize rs2
add x25, x0, x24 # perform operation
RVTEST_SIGUPD(x3, x25)

# Testcase cp_rs1 (Test source rs1 = x1)
li x1, 0x81c4ef2a # initialize rs1
li x6, 0x917cfa69 # initialize rs2
add x7, x1, x6 # perform operation
RVTEST_SIGUPD(x3, x7)

...

# Testcase cp_rs1 (Test source rs1 = x31)
mv x21, x31 # switch signature pointer register to avoid conflict with test
li x31, 0x1508dd4e # initialize rs1
li x14, 0x830d07b0 # initialize rs2
add x11, x31, x14 # perform operation
RVTEST_SIGUPD(x21, x11)


# Testcase cp_rd (Test destination rd = x0)
li x19, 0x1d01c852 # initialize rs1
li x9, 0x1bfbf146 # initialize rs2
add x0, x19, x9 # perform operation
RVTEST_SIGUPD(x20, x0)

# Testcase cp_rd (Test destination rd = x1)
li x26, 0x1e3aafcf # initialize rs1
li x19, 0x986da37b # initialize rs2
add x1, x26, x19 # perform operation
RVTEST_SIGUPD(x20, x1)

...

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x0)
li x15, 0x00000000 # initialize rs1
li x5, 0x00000000 # initialize rs2
add x11, x15, x5 # perform operation
RVTEST_SIGUPD(x10, x11)

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x1)
li x1, 0x00000000 # initialize rs1
li x31, 0x00000001 # initialize rs2
add x20, x1, x31 # perform operation
RVTEST_SIGUPD(x10, x20)

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x2)
li x27, 0x00000000 # initialize rs1
li x3, 0x00000002 # initialize rs2
add x11, x27, x3 # perform operation
RVTEST_SIGUPD(x10, x11)

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x80000000)
li x8, 0x00000000 # initialize rs1
li x5, 0x80000000 # initialize rs2
add x16, x8, x5 # perform operation
RVTEST_SIGUPD(x10, x16)

A.2. Test case example: cr_rs1_rs2_edges bin with rs1 = 0x0, rs2 = 0x80000000

# Testcase cr_rs1_rs2_edges (Test source rs1 = 0x0 rs2 = 0x80000000)
li x8, 0x00000000 # initialize rs1 in randomly selected register
li x5, 0x80000000 # initialize rs2 in randomly selected register
add x16, x8, x5 # perform operation, write randomly selected destination register
# load expected value of 0x800000000 into x20 from table pointed to by x10. Check x20 against x16 and report mismmatch
RVTEST_SIGUPD(x10, x16, x20)

RVTEST_SIGUPD macro:

if (RVTEST_SELFCHECK) # check result against signature
    LREG x20, 0(x10)
    beq x16, x20, 1f
    ecall
    1f:
else # generate signature
    SREG x16, 0(x10)
    addi x10, x10, WORDSIZE
    nop

1. Extended RVVI adds signals for virtual memory verification, including physical and virtual instruction and data addresses, and I/D TLB entries.

2. Portions of riscvISACOV that depend on proprietary Synopsys code such as a disassembler have been replaced with open-source equivalents

3. Tentative; may need updating based on the MRD Market Requirements Document

4. cp_asm_count is an exception, just counting the number of times the instruction was executed

5. Certain instructions are omitted if not supported for a given SEW. For example, widening add vwadd.vv is not supported for SEW=64, and vrgatherei16.v is not supported for SEW=8.